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TMS320F2802x Piccolo 技术参考手册:系统控制与中断
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"TMS320F2802x, TMS320F2802xx Piccolo 技术参考手册"
这本技术参考手册是针对Texas Instruments(TI)的TMS320F2802x系列微控制器的详细指南,它包含了该系列芯片的系统控制、中断处理、内存结构、安全特性、时钟系统以及通用输入/输出(GPIO)等多个关键领域的全面信息。TMS320F2802x系列属于Piccolo微控制器家族,适用于需要高性能、低功耗解决方案的应用。
1. **系统控制和中断**
- **闪存和OTP内存块**:手册详细介绍了闪存和一次性可编程(OTP)内存的功能和操作。闪存用于存储程序代码,而OTP内存常用于存储固定配置数据或密钥。
- **闪存和OTP电源模式**:讨论了在不同电源状态下,如何管理和优化这两种内存的功耗。
- **闪存和OTP寄存器**:列出了相关的寄存器,这些寄存器用于控制和监控内存的操作。
2. **代码安全模块(CSM)**
- **功能描述**:解释了CSM如何保护代码免受未经授权的访问。
- **CSM对其他片上资源的影响**:讨论了CSM如何与其他硬件模块交互,以确保整个系统的安全性。
- **在用户应用中集成代码安全**:提供了在设计中整合CSM特性的指导。
- **保护安全逻辑的注意事项**:给出了确保CSM功能正常运行的建议和避免潜在问题的提示。
- **CSM功能概述**:总结了CSM的主要特性,如加密、解密和安全启动等。
3. **时钟系统**
- **时钟和系统控制**:描述了如何配置和管理芯片的时钟源,以满足不同应用的需求。
- **OSC和PLL块**:详细讲解了振荡器(OSC)和锁相环(PLL)的工作原理,它们是调整系统时钟频率的关键部件。
- **低功耗模式块**:介绍了不同低功耗模式,以在不影响性能的情况下降低功耗。
- **CPU看门狗块**:阐述了CPU看门狗定时器的作用,它用于防止程序因故障而无限循环。
- **32位CPU计时器0/1/2**:详细说明了这些计时器的用法,它们可以用于定时任务、事件检测等。
4. **通用输入/输出(GPIO)**
- **GPIO模块概述**:提供了GPIO的基本功能和使用场景的概览。
- **配置概述**:涵盖了GPIO引脚的配置选项,包括输入输出模式、驱动强度和上拉下拉电阻。
- **数字通用I/O控制**:解释了如何控制GPIO引脚的状态。
- **输入资格**:讨论了输入信号的采样和滤波机制,以确保数据的准确读取。
- **GPIO和外设复用(MUX)**:说明了如何将GPIO引脚与多个外设功能共享,以提高资源利用率。
- **寄存器描述**:列出了GPIO相关的控制寄存器,用于设置和读取引脚状态。
这个手册是开发人员理解和利用TMS320F2802x系列微控制器功能的重要参考资料,结合数据手册使用,能更深入地了解和优化系统设计。
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SPRUI09–December 2018
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List of Figures
9-22. SCIFFCT Register ........................................................................................................ 517
9-23. SCIPRI Register .......................................................................................................... 518
10-1. Multiple I2C Modules Connected ....................................................................................... 520
10-2. I2C Module Conceptual Block Diagram................................................................................ 522
10-3. Clocking Diagram for the I2C Module.................................................................................. 522
10-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH) .................................................... 523
10-5. Bit Transfer on the I2C bus.............................................................................................. 524
10-6. I2C Module START and STOP Conditions............................................................................ 526
10-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)............................. 527
10-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................. 527
10-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ............................................ 527
10-10. I2C Module Free Data Format (FDF = 1 in I2CMDR)................................................................ 528
10-11. Repeated START Condition (in This Case, 7-Bit Addressing Format) ............................................ 528
10-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................. 529
10-13. Arbitration Procedure Between Two Master-Transmitters........................................................... 530
10-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit....................................... 531
10-15. Enable Paths of the I2C Interrupt Requests .......................................................................... 532
10-16. Backwards Compatibility Mode Bit, Slave Transmitter............................................................... 533
10-17. I2C FIFO Interrupt ........................................................................................................ 534
10-18. I2COAR Register ......................................................................................................... 537
10-19. I2CIER Register........................................................................................................... 538
10-20. I2CSTR Register.......................................................................................................... 539
10-21. I2CCLKL Register ........................................................................................................ 543
10-22. I2CCLKH Register ........................................................................................................ 544
10-23. I2CCNT Register.......................................................................................................... 545
10-24. I2CDRR Register ......................................................................................................... 546
10-25. I2CSAR Register.......................................................................................................... 547
10-26. I2CDXR Register.......................................................................................................... 548
10-27. I2CMDR Register ......................................................................................................... 549
10-28. I2CISRC Register......................................................................................................... 553
10-29. I2CEMDR Register ....................................................................................................... 554
10-30. I2CPSC Register.......................................................................................................... 555
10-31. I2CFFTX Register ........................................................................................................ 556
10-32. I2CFFRX Register ........................................................................................................ 558
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SPRUI09–December 2018
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List of Tables
List of Tables
1-1. Flash/OTP Configuration Registers...................................................................................... 33
1-2. Flash Options Register (FOPT) Field Descriptions .................................................................... 34
1-3. Flash Power Register (FPWR) Field Descriptions ..................................................................... 34
1-4. Flash Status Register (FSTATUS) Field Descriptions................................................................. 35
1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 36
1-6. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions............................. 36
1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 37
1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 38
1-9. Security Levels ............................................................................................................. 39
1-10. Resources Affected by the CSM ......................................................................................... 41
1-11. Resources Not Affected by the CSM .................................................................................... 41
1-12. Code Security Module (CSM) Registers ................................................................................ 42
1-13. CSM Status and Control Register (CSMSCR) Field Descriptions ................................................... 43
1-14. PLL, Clocking, Watchdog, and Low-Power Mode Registers ......................................................... 48
1-15. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions................................................ 49
1-16. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 50
1-17. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions................................................ 51
1-18. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions................................................ 51
1-19. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions................................... 52
1-20. Internal Oscillator Trim (INTOSCnTRIM) Register Field Descriptions .............................................. 54
1-21. Clocking (XCLK) Field Descriptions ..................................................................................... 55
1-22. Clock Control (CLKCTL) Register Field Descriptions ................................................................. 55
1-23. Possible PLL Configuration Modes ...................................................................................... 58
1-24. PLL Settings ................................................................................................................ 61
1-25. PLL Status Register (PLLSTS) Field Descriptions..................................................................... 61
1-26. PLL Lock Period (PLLLOCKPRD) Register Field Descriptions ...................................................... 63
1-27. NMI Interrupt Registers.................................................................................................... 68
1-28. NMI Configuration (NMICFG) Register Bit Definitions (EALLOW)................................................... 69
1-29. NMI Flag (NMIFLG) Register Bit Definitions (EALLOW Protected).................................................. 69
1-30. NMI Flag Clear (NMIFLGCLR) Register Bit Definitions (EALLOW Protected)..................................... 70
1-31. NMI Flag Force (NMIFLGFRC) Register Bit Definitions (EALLOW Protected) .................................... 71
1-32. NMI Watchdog Counter (NMIWDCNT) Register Bit Definitions...................................................... 71
1-33. NMI Watchdog Period (NMIWDPRD) Register Bit Definitions (EALLOW Protected) ............................. 71
1-34. Low-Power Mode Summary .............................................................................................. 74
1-35. Low Power Modes ......................................................................................................... 74
1-36. Low-Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 75
1-37. Example Watchdog Key Sequences..................................................................................... 77
1-38. System Control and Status Register (SCSR) Field Descriptions .................................................... 79
1-39. Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 80
1-40. Watchdog Reset Key Register (WDKEY) Field Descriptions......................................................... 80
1-41. Watchdog Control Register (WDCR) Field Descriptions .............................................................. 80
1-42. CPU-Timers 0, 1, 2 Configuration and Control Registers............................................................. 83
1-43. TIMERxTIM Register Field Descriptions ................................................................................ 83
1-44. TIMERxTIMH Register Field Descriptions .............................................................................. 84
1-45. TIMERxPRD Register Field Descriptions ............................................................................... 84
1-46. TIMERxPRDH Register Field Descriptions ............................................................................. 84
1-47. TIMERxTCR Register Field Descriptions ............................................................................... 84
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SPRUI09–December 2018
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List of Tables
1-48. TIMERxTPR Register Field Descriptions ............................................................................... 85
1-49. TIMERxTPRH Register Field Descriptions.............................................................................. 86
1-50. JTAGDEBUG Register Field Descriptions .............................................................................. 91
1-51. GPIO Control Registers ................................................................................................... 93
1-52. GPIO Interrupt and Low Power Mode Select Registers............................................................... 93
1-53. GPIO Data Registers ...................................................................................................... 95
1-54. Sampling Period............................................................................................................ 98
1-55. Sampling Frequency ....................................................................................................... 98
1-56. Case 1: Three-Sample Sampling Window Width ...................................................................... 98
1-57. Case 2: Six-Sample Sampling Window Width.......................................................................... 99
1-58. Default State of Peripheral Input........................................................................................ 102
1-59. 2802x GPIOA MUX....................................................................................................... 103
1-60. 2802x GPIOB MUX....................................................................................................... 104
1-61. Analog MUX ............................................................................................................... 105
1-62. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions............................................. 105
1-63. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ..................................................... 107
1-64. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ..................................................... 108
1-65. Analog I/O MUX (AIOMUX1) Register Field Descriptions........................................................... 109
1-66. GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions ..................................... 109
1-67. GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions ..................................... 111
1-68. GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions................................... 112
1-69. GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions................................... 113
1-70. GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions................................... 114
1-71. GPIO Port A Direction (GPADIR) Register Field Descriptions...................................................... 114
1-72. GPIO Port B Direction (GPBDIR) Register Field Descriptions...................................................... 115
1-73. Analog I/O DIR (AIODIR) Register Field Descriptions ............................................................... 116
1-74. GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 116
1-75. GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 117
1-76. GPIO Port A Data (GPADAT) Register Field Descriptions.......................................................... 118
1-77. GPIO Port B Data (GPBDAT) Register Field Descriptions.......................................................... 118
1-78. Analog I/O DAT (AIODAT) Register Field Descriptions ............................................................. 119
1-79. GPIO Port A Set (GPASET) Register Field Descriptions............................................................ 119
1-80. GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 119
1-81. GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 120
1-82. GPIO Port B Set (GPBSET) Register Field Descriptions............................................................ 120
1-83. GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 120
1-84. GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 121
1-85. Analog I/O Set (AIOSET) Register Field Descriptions ............................................................... 121
1-86. Analog I/O Clear (AIOCLEAR) Register Field Descriptions......................................................... 121
1-87. Analog I/O Toggle (AIOTOGGLE) Register Field Descriptions..................................................... 121
1-88. GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions..................................... 122
1-89. XINT1/XINT2/XINT3 Interrupt Select and Configuration Registers ................................................ 122
1-90. GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions.......................... 123
1-91. Peripheral Frame 0 Registers .......................................................................................... 124
1-92. Peripheral Frame 1 Registers........................................................................................... 125
1-93. Peripheral Frame 2 Registers........................................................................................... 125
1-94. Access to EALLOW-Protected Registers.............................................................................. 126
1-95. EALLOW-Protected Device Emulation Registers..................................................................... 126
1-96. EALLOW-Protected Flash/OTP Configuration Registers............................................................ 126
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SPRUI09–December 2018
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List of Tables
1-97. EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 127
1-98. EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 127
1-99. EALLOW-Protected GPIO Registers................................................................................... 128
1-100. EALLOW-Protected PIE Vector Table ................................................................................. 129
1-101. EALLOW-Protected ePWM1 - ePWM 7 Registers ................................................................... 129
1-102. Device Emulation Registers ............................................................................................. 130
1-103. DEVICECNF Register Field Descriptions.............................................................................. 130
1-104. PARTID Register Field Descriptions ................................................................................... 131
1-105. CLASSID Register Field Descriptions.................................................................................. 131
1-106. REVID Register Field Descriptions..................................................................................... 132
1-107. Enabling Interrupt ......................................................................................................... 136
1-108. Interrupt Vector Table Mapping ........................................................................................ 137
1-109. Vector Table Mapping After Reset Operation ........................................................................ 137
1-110. PIE MUXed Peripheral Interrupt Vector Table ........................................................................ 143
1-111. PIE Vector Table.......................................................................................................... 144
1-112. PIE Configuration and Control Registers .............................................................................. 148
1-113. PIECTRL Register Address Field Descriptions ....................................................................... 149
1-114. PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions................................................. 149
1-115. PIEIFRx Register Field Descriptions ................................................................................... 150
1-116. PIEIERx Register (x = 1 to 12) Field Descriptions ................................................................... 151
1-117. Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 152
1-118. Interrupt Enable Register (IER) — CPU Register Field Descriptions.............................................. 154
1-119. Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 155
1-120. Interrupt Control and Counter Registers (not EALLOW Protected) ................................................ 157
1-121. External Interrupt n Control Register (XINTnCR) Field Descriptions .............................................. 157
1-122. External Interrupt n Counter (XINTnCTR) Field Descriptions....................................................... 158
1-123. BOR Configuration (BORCFG) Field Descriptions ................................................................... 160
2-1. Vector Locations .......................................................................................................... 166
2-2. Configuration for Device Modes ........................................................................................ 168
2-3. PIE Vector SARAM Locations Used by the Boot ROM.............................................................. 170
2-4. Boot Mode Selection ..................................................................................................... 170
2-5. Valid EMU_KEY and EMU_BMODE Values .......................................................................... 172
2-6. OTP Values for GetMode................................................................................................ 174
2-7. Emulation Boot Modes (TRST = 1)..................................................................................... 175
2-8. Standalone Boot Modes with (TRST = 0) ............................................................................. 176
2-9. LSB/MSB Loading Sequence in 8-bit Data Stream .................................................................. 177
2-10. Parallel GPIO Boot 8-Bit Data Stream ................................................................................. 186
2-11. SPI 8-Bit Data Stream ................................................................................................... 191
2-12. I2C 8-Bit Data Stream.................................................................................................... 196
2-13. CPU Register Restored Values......................................................................................... 198
2-14. Bootloader Options ....................................................................................................... 199
2-15. Bootloader Revision and Checksum Information..................................................................... 202
2-16. Bootloader Revision Per Device ........................................................................................ 202
3-1. ePWM Module Control and Status Register Set Grouped by Submodule ........................................ 208
3-2. Submodule Configuration Parameters ................................................................................. 210
3-3. Time-Base Submodule Registers....................................................................................... 213
3-4. Key Time-Base Signals .................................................................................................. 214
3-5. Counter-Compare Submodule Registers ............................................................................. 222
3-6. Counter-Compare Submodule Key Signals ........................................................................... 223
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List of Tables
3-7. Action-Qualifier Submodule Registers ................................................................................. 228
3-8. Action-Qualifier Submodule Possible Input Events .................................................................. 229
3-9. Action-Qualifier Event Priority for Up-Down-Count Mode ........................................................... 231
3-10. Action-Qualifier Event Priority for Up-Count Mode ................................................................... 231
3-11. Action-Qualifier Event Priority for Down-Count Mode................................................................ 231
3-12. Behavior if CMPA/CMPB is Greater than the Period ................................................................ 231
3-13. Dead-Band Generator Submodule Registers ......................................................................... 242
3-14. Classical Dead-Band Operating Modes ............................................................................... 244
3-15. PWM-Chopper Submodule Registers.................................................................................. 247
3-16. Possible Pulse Width Values for SYSCLKOUT = 90 MHz .......................................................... 249
3-17. Trip-Zone Submodule Registers........................................................................................ 252
3-18. Possible Actions On a Trip Event....................................................................................... 254
3-19. Event-Trigger Submodule Registers .................................................................................. 258
3-20. Digital Compare Submodule Registers ................................................................................ 261
3-21. Time-Base Period Register (TBPRD) Field Descriptions............................................................ 294
3-22. Time Base Period High Resolution Register (TBPRDHR) Field Descriptions .................................... 294
3-23. Time Base Period Mirror Register (TBPRDM) Field Descriptions.................................................. 295
3-24. Time-Base Period High Resolution Mirror Register (TBPRDHRM) Field Descriptions.......................... 295
3-25. Time-Base Phase Register (TBPHS) Field Descriptions ............................................................ 295
3-26. Time-Base Phase High Resolution Register (TBPHSHR) Field Descriptions .................................... 296
3-27. Time-Base Counter Register (TBCTR) Field Descriptions .......................................................... 296
3-28. Time-Base Control Register (TBCTL) Field Descriptions ........................................................... 296
3-29. Time-Base Status Register (TBSTS) Field Descriptions ............................................................ 299
3-30. High Resolution Period Control Register (HRPCTL) Field Descriptions .......................................... 299
3-31. Counter-Compare A Register (CMPA) Field Descriptions........................................................... 301
3-32. Counter-Compare B Register (CMPB) Field Descriptions........................................................... 302
3-33. Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................ 303
3-34. Compare A High Resolution Register (CMPAHR) Field Descriptions ............................................. 304
3-35. Counter-Compare A Mirror Register (CMPAM) Field Descriptions ................................................ 304
3-36. Compare A High-Resolution Mirror Register (CMPAHRM) Field Descriptions ................................... 305
3-37. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions ....................................... 305
3-38. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions ....................................... 306
3-39. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions.......................................... 307
3-40. Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions.......................... 308
3-41. Dead-Band Generator Control Register (DBCTL) Field Descriptions.............................................. 309
3-42. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ............................... 310
3-43. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ............................... 310
3-44. PWM-Chopper Control Register (PCCTL) Bit Descriptions ........................................................ 311
3-45. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ............................................... 313
3-46. Trip-Zone Control Register Field Descriptions........................................................................ 314
3-47. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ................................................. 315
3-48. Trip-Zone Flag Register Field Descriptions ........................................................................... 316
3-49. Trip-Zone Clear Register (TZCLR) Field Descriptions............................................................... 317
3-50. Trip-Zone Force Register (TZFRC) Field Descriptions .............................................................. 317
3-51. Trip Zone Digital Compare Event Select Register (TZDCSEL) Field Descriptions .............................. 318
3-52. Digital Compare Trip Select (DCTRIPSEL) Field Descriptions ..................................................... 320
3-53. Digital Compare A Control Register (DCACTL) Field Descriptions ................................................ 321
3-54. Digital Compare B Control Register (DCBCTL) Field Descriptions ................................................ 322
3-55. Digital Compare Filter Control Register (DCFCTL) Field Descriptions ............................................ 322
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