"TDP142 DP转接驱动器：高性能DP接收机与GPU扩展"

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The TI-TDP142 is a DP (DisplayPort) to DP scaler designed to provide high-quality video and audio output for a variety of applications. This versatile device features a receptacle for easy connection to various devices and interfaces, including ML_IN, ML_OUT, and AUX connections. The TDP142DP Receptacle is capable of receiving input from multiple sources, such as ML_IN, ML1_IN, ML2_IN, ML3_IN, as well as transmitting output to ML0_OUT, ML1_OUT, ML2_OUT, and ML3_OUT. The TDP142DP Receptacle is equipped with a built-in driver that allows for seamless integration with GPUs and other devices. This driver ensures optimal performance and compatibility, making it an ideal solution for high-performance computing and multimedia applications. The TDP142DP Receptacle also features an AUX connection for additional functionality and enhanced control options. The TDP142DP Receptacle is part of the TDP142 series, which is designed and manufactured by Texas Instruments Incorporated. This series includes a range of scalers and other products that are engineered to deliver superior performance and reliability. The TDP142DP Receptacle is copyright protected and is intended for use with GPUs and other compatible devices. In summary, the TDP142DP Receptacle is a versatile and high-performance DP to DP scaler that offers a wide range of features and functionality. Its advanced driver technology, multiple input and output options, and copyright protection make it an ideal solution for a variety of applications. Whether used for gaming, multimedia production, or professional computing, the TDP142DP Receptacle delivers superior performance and quality. For more information on the TDP142DP Receptacle and other products in the TDP142 series, visit Texas Instruments' website to access technical documents and tools for ordering.

TDP142

www.ti.com.cn

ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DisplayPort Transmitter (OUTDP[3:0]p or OUTDP[3:0]n)

TX(DIFF-PP)

Transmitter dynamic differential voltage swing range. 1500 mV

TX(RCV-DETECT)

Amount of voltage change allowed during receiver detection 600 mV

TX(CM-AC-PP-ACTIVE)

Tx AC common-mode voltage active

Max mismatch from Txp + Txn for both

time and amplitude

100 mV

TX(IDLE-DIFF-AC-PP)

AC electrical idle differential peak-to-

peak output voltage

At package pins 0 10 mV

TX(IDLE-DIFF-DC)

DC electrical idle differential output

voltage

At package pins after low pass filter to

remove AC component

0 14 mV

TX(DIFF)

Differential impedance of the driver 75 120 Ω

AC(COUPLING)

AC coupling capacitor 75 265 nF

TX(CM)

Common-mode impedance of the

driver

Measured with respect to AC ground

over

0–500 mV

18 30 Ω

TX(PARASITIC)

TX input capacitance for return loss At package pins, at 2.5GHz 1.25 pF

LTX(DIFF)

Differential return loss

50 MHz – 1.25 GHz at 90 Ω -15 dB

2.5 GHz at 90 Ω -12 dB

LTX(CM)

Common-mode return loss 50 MHz – 2.5 GHz at 90 Ω -13 dB

TX(SHORT)

TX short circuit current TX± shorted to GND 67 mA

TX(DC-CM)

Common-mode voltage bias in the transmitter (DC) 0 0 V

AC Characteristics

Crosstalk

Differential crosstalk between TX and

RX signal pairs

at 2.5 GHz –30 dB

(P1dB-LF)

Low frequency 1-dB compression

point

at 100 MHz, 200 mV

< V

< 2000 mV

1300 mV

(P1dB-HF)

High frequency 1-dB compression

point

at 2.5 GHz, 200 mV

< V

< 2000 mV

1300 mV

Low frequency cutoff 200 mV

< V

< 2000 mV

20 50 kHz

TX output deterministic jitter

200 mV

< V

< 2000 mV

, PRBS7,

5 Gbps

0.05 UIpp

200 mV

< V

< 2000 mV

, PRBS7,

8.1 Gbps

0.08 UIpp

TX output total jitter

200 mV

< V

< 2000 mV

, PRBS7,

5 Gbps

0.08 UIpp

200 mV

< V

< 2000 mV

, PRBS7,

8.1 Gbps

0.135 UIpp

DisplayPort Receiver (INDP[3:0]p or INDP[3:0]n)

ID(PP)

Peak-to-peak input differential dynamic voltage range 2000 V

Input common mode voltage 0 2 V

(AC)

AC coupling capacitance 75 200 nF

Q(DP)

Receiver equalization DPEQ[1:0] at 4.05 GHz 14 dB

Data rate HBR3 8.1 Gbps

(ti)

Input termination resistance 80 100 120 Ω

AUXp or AUXn

(AUXP_DC_CM)

AUX Channel DC common mode

voltage for AUXp

= 3.3 V 0 0.4 V

(AUXN_DC_CM)

AUX Channel DC common mode

voltage for AUXn

= 3.3 V 2.7 3.6 V

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