"HDMI重定时器TI-TMDS181.pdf详解及控制方法"

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TI-TMDS181.pdf是一份关于HDMI重定时器的技术文档。该文档介绍了TI-TMDS181的详细规格和功能。 TI-TMDS181是一款高性能的HDMI重定时器，它可用于音视频处理单元和数字电视等设备中。该芯片拥有多种输入和输出接口，能够实现高质量的音视频信号传输和处理。它支持多种视频和音频格式，如TMDS、ARC和SPDIF等。 TI-TMDS181的输入接口包括IN_CLKp、IN_CLKn、IN_D[2:0]p和IN_D[2:0]n等。这些接口用于接收来自外部设备的HDMI信号。通过对输入信号进行预处理和重定时，可以提高信号的稳定性和质量。 TI-TMDS181还具有多个数据寄存器，用于存储和处理输入信号的数据。这些寄存器能够实现数据传输的控制和调整。同时，该芯片还支持信号的交换和极性调整，以适应不同设备的需求。 TI-TMDS181的输出接口包括OUT_CLKp、OUT_D[2:0]p、OUT_CLKn和OUT_D[2:0]n等。通过这些接口，可以将处理后的音视频信号输出到显示设备或其他外部设备。为了保证信号传输的稳定性，TI-TMDS181还支持均衡和预失真等特性。通过设置EQ和SDA_CTL等参数，可以有效地调整信号波形，以消除传输中的失真和干扰。此外，TI-TMDS181还支持HDCP和DDC等功能。HDCP是一种用于保护数字内容的加密技术，能够实现高质量的数字音视频传输。DDC则是用于设备之间进行通信和控制的接口。 TI-TMDS181的控制部分包括多个寄存器和控制模块。通过对这些寄存器和模块的设置，可以实现对芯片功能和参数的灵活控制。同时，该芯片还支持I2C通信协议，可以通过I2C控制器与其他设备进行通信。总之，TI-TMDS181是一款功能强大的HDMI重定时器芯片。它具有多种输入和输出接口，支持高质量的音视频传输和处理。通过对信号的调整和控制，可以实现稳定、高清的音视频显示效果。它在数字电视和音视频处理领域具有广泛的应用前景。

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TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

(1) The typical rating is simulated at 3.3 V V

and 1.2 V V

and at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V

and 1.27 V V

and at 85°C unless otherwise noted

6.7 TMDS Differential Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX

(2)

UNIT

Single-ended high level output

voltage

Data rate ≤1.65 Gbps

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; DR = 750 Mbps; VSadj = 7.06 kΩ;

– 10 V

+ 10

Single-ended high level output

voltage

Data rate >1.65 Gbps and

<3.4 Gbps

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;

-200 V

+ 10

Single-ended high level output

voltage

Data rate >3.4 Gbps and < 6

Gbps

(2)

PRE_SEL = NC; TX_TERM_CTL = L; OE

= H; DR = 6 Gbps; VSadj = 7.06 kΩ;

– 400 V

+ 10

Single-ended low level output

voltage

Data rate ≤1.65 Gbps

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; DR = 750 Mbps; VSadj = 7.06 kΩ;

– 600 V

– 400

Single-ended low level output

voltage

Data rate >1.65 Gbps and

<3.4 Gbps

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;

– 700 V

– 400

Single-ended low level output

voltage

Data rate >3.4 Gbps and < 6

Gbps

(2)

PRE_SEL = NC; TX_TERM_CTL = L; OE

= H; DR = 6 Gbps; VSadj = 7.06 kΩ;

– 1000 V

– 400

SWING_DA

Single-ended output voltage

swing on data lane

PRE_SEL = NC; TX_TERM_CTL =

H/NC/L; OE = H; DR = 270 Mbps/2.97/6

Gbps VSadj = 7.06 kΩ;

400 500 600 mV

SWING_CLK

Single-ended output voltage

swing on clock lane

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; Data rate ≤ 3.4 Gbps; VSadj = 7.06

kΩ;

400 500 600

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; Data rate > 3.4 Gbps; VSadj =

7.06 kΩ;

200 300 400

ΔV

SWING

Change in single-end output

voltage swing per 100 Ω

ΔVSadj

20 mV

ΔV

OCM(SS)

Change in steady state output

common mode voltage

between logic levels

–5 5 mV

OD(PP)

Output differential voltage

before pre-emphasis

SADJ

= 7.06 kΩ; PRE_SEL = NC see

Figure 10

800 1200 mV

OD(SS)

Steady state output differential

voltage

SADJ

= 7.06 kΩ; PRE_SEL = L, see

Figure 11

600 1075 mV

OD_range

Total TMDS data lanes output

differential voltage for

HDMI2.0. Retimer Mode Only

See Figure 14

3.4 Gbps < R

bit

≤ 3.712 Gps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

335

3.712 Gbps < R

bit

< 5.94 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

–19.66 ×

bit

) +

(106.74 × R

bit

)

+ 209.58

5.94 Gbps ≤ R

bit

≤ 6.0 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

150

Short-circuit current limit Main link output shorted to GND 50 mA

LEAK

Failsafe condition leakage

current

= 0 V; V

= 0 V; TMDS Outputs

pulled to 3.3 V through 50 Ω resistor;

45 μA

TERM

Source termination resistance

for HDMI2.0

75 150 Ω

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

(1) The typical rating is simulated at 3.3 V V

and 1.2 V V

and at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V

and 1.27 V V

and at 85°C unless otherwise noted

6.8 DDC, I

C, HPD, and ARC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX

(2)

UNIT

DDC AND I

I-DC

SCL/SDA_SNK, SCL/SDA_SRC DC

input voltage

–0.3 5.5 V

SCL/SDA_CTL, DC input voltage –0.3 3.6 V

SCL/SDA_SNK, SCL/SDA_SRC Low

level input voltage

0.3 x V

SCL/SDA_CTL Low level input

voltage

0.3 x V

SCL/SDA_SNK, SCL/SDA_SRC high

level input voltage

3 V

SCL/SDA_CTL high level input

voltage

0.7 x V

SCL/SDA_CTL, SCL/SDA_SRC low

level output voltage

= 3 mA and V

> 2 V 0.4

= 3 mA and V

< 2 V 0.2 x V

SCL

SCL clock frequency fast I2C mode

for local I2C control

400 kHz

bus

Total capacitive load for each bus line

(DDC and local I2C pins)

400 pF

HPD

High-level input voltage HPD_SNK 2.1 V

Low-level input voltage HPD_SNK 0.8 V

High-level output voltage I

= –500 µA; HPD_SRC, 2.4 3.6 V

Low-level output voltage I

= 500 µA; HPD_SRC, 0 0.1 V

LEAK

Failsafe condition leakage current

= 0 V; V

= 0 V; HPD_SNK =

5 V;

40 μA

H_HPD

High-level input current

Device powered; V

= 5 V;

H_HPD

includes R

pdHPD

resistor

current

µA

Device powered; V

= 0.8 V;

L_HPD

includes R

pdHPD

resistor

current

pdHPD

HPD input termination to GND V

= 0 V 150 190 220 kΩ

SPDIF AND ARC

Operating DC voltage for single mode

ARC output

Test at ARC_OUT, see Figure 22 0 5 V

IN_DC

Operating DC voltage for SPDIF input 0.05 V

SP_SW

Signal amplitude of SPDIF input 0.2 0.5 0.6 V

ElSWING

Signal amplitude on the ARC output

Test at ARC_OUT, 55 Ω external

termination resistor, see Figure 22

0.4 0.5 0.6 V

CLK_ARC Signal frequency on ARC Test at ARC_OUT, see Figure 22 3.687

5.645

±0.1%

13.517 MHz

Duty cycle Output clock duty cycle 45% 50% 55%

Data rate SPDIF input DR 7.373 11.29 27.034 Mbps

EDGE

Rise/fall time for ARC output From 10% to 90% voltage level 0.4 UI

_IN_SPDIF

Input termination resistance for

SPDIF

75 Ω

est

Single mode output termination

resistance

0.1 MHz to 128× the maximum

frame rate

36 55 75 Ω

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