片上网络（Network-on-Chip）：架构与路由器算法

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"NETWORK-ON-CHIP - 片上网络基础知识，主要涵盖路由器设计、算法以及工作原理。" "Network-on-Chip (NoC) 架构是现代集成电路设计中的一个重要概念，它作为一种通信基础设施，取代了传统的互连方式，如总线和多端口存储器，以解决芯片上不断增加的并行性和复杂性。NoC的基本思想是通过构建一个分布式的、通信导向的网络来连接芯片上的各个处理元素，从而实现更高效的数据传输和资源共享。在NoC架构中，路由器是核心组件，它们负责数据包的转发和路由决策。路由器通常包括输入、输出缓冲区，以及一个路由单元，用于根据网络拓扑和协议选择最佳路径。设计路由器时，需要考虑的关键因素包括功耗、延迟、吞吐量和可扩展性。例如，采用 XY 路由、虚拟通道、分布式仲裁等策略可以优化这些性能指标。算法设计在NoC中扮演着至关重要的角色。这包括路由算法（如XY、Z、曼哈顿、最短路径等）、流量控制算法（用于防止拥塞和保证服务质量）以及错误检测和恢复策略。例如，基于信誉的路由算法可以在网络动态变化时提供鲁棒性，而自适应路由可以应对负载变化。 NoC的工作原理涉及到多个层面，从物理层的信号传输到网络层的协议执行。物理层关注信号质量和传输速率，而数据链路层则负责帧的打包和解包。网络层处理路由选择，传输层可能包括流控制和拥塞控制机制。应用层则根据具体任务需求，如多媒体处理、计算密集型应用等，利用NoC提供的服务进行通信。 NoC的设计探索是全方位的，需要综合考虑硬件、软件和系统层面的挑战。设计者需要平衡性能、功耗、面积和可靠性等多个因素，以满足不同应用场景的需求。此外，随着物联网和云计算的发展，NoC技术也正逐渐向异构计算、安全性和能效优化等方向发展。 NoC架构为片上系统的互连提供了高效、灵活的解决方案，但同时也带来了复杂的设计挑战。深入理解NoC的基础知识，包括其路由器设计、算法设计和工作原理，对于推动集成电路的创新至关重要。"

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BookID 186671_ChapID FM1_Proof# 1 - 28/08/2009

List of Figures

Fig. 6.11 The VA Compaction Architecture................................................... 109

Fig. 6.12 The Staggered Arbitration Mechanism Employed by

the VA Compaction Architecture .................................................... 110

Fig. 6.13 Effect of No-Grants on Generic and VA Compaction Modules ..... 111

Fig. 6.14 The SA Folding Concept ................................................................ 112

Fig. 6.15 Detailed View of the SA Folding Architecture ............................... 113

Fig. 6.16 Effect of No-Grants on Generic and SA Folding Modules ............. 114

Fig. 7.1 Bus Segmentation ........................................................................... 122

Fig. 7.2 Unfairness Caused by Timeslice Reassignment ............................. 123

Fig. 7.3 Normalized CDMA Throughput Using Walsh

Orthogonal Codes ........................................................................... 126

Fig. 7.4 Example of Dynamic Timeslot Allocation ..................................... 128

Fig. 7.5 Architecture of the dTDMA Receiver and Transmitter .................. 129

Fig. 7.6 A Simple 2-PE Transfer on dTDMA and AMBA .......................... 131

Fig. 7.7 dTDMA Bus Throughput (Uniform Injection) ............................... 133

Fig. 7.8 Unicast Latencies for Several Bus Sizes ......................................... 134

Fig. 7.9 Latency Using Three Different Arbitration Policies ....................... 136

Fig. 7.10 Power Consumption of the dTDMA Bus ........................................ 137

Fig. 7.11 dTDMA Bus vs. NoC Latencies for Uniform (a-d)

and Multimedia (e-h) Trafﬁc Injection. A Comparison

of Average Power Consumption is Shown in (i). ............................ 140

Fig. 7.12 Hybridization of the AG Mesh Using the dTDMA Bus ................. 143

Fig. 7.13 Hybrid dTDMA Bus/NoC vs. Pure NoC (AG Mesh)

Latencies for Uniform (a-c) and Multimedia (d-f)

Trafﬁc Injection ............................................................................... 145

Fig. 7.14 Hybrid dTDMA Bus/NoC vs. Pure NoC (AG Mesh)

Average Power Consumption (Uniform Trafﬁc Injection) ............. 145

Fig. 8.1 The Progression from 2D Hybridization in Chapter 7 to

3D Hybridization in Chapter 8. ....................................................... 148

Fig. 8.2 Wiring Scales in Length as the Square Root of the

Number of Layers in Three Dimensions ......................................... 151

Fig. 8.3 Face-to-Face and Face-to-Back Wafer-Bonding in

3D Technology ................................................................................ 152

Fig. 8.4 The Proposed 3D Network-In-Memory (NetInMem)

Architecture ..................................................................................... 154

Fig. 8.5 Transceiver Module of a dTDMA Bus ........................................... 155

Fig. 8.6 Side View of the 3D Chip with the dTDMA Bus (Pillar) ............... 156

Fig. 8.7 A High-Level Overview of the Modiﬁed Router of the

Pillar Nodes ..................................................................................... 158

Fig. 8.8 A CPU has More Cache Banks in its Vicinity in the

3D Architecture ............................................................................... 158

Fig. 8.9 Hotspots can be Avoided by Offsetting CPUs in All

Three Dimensions ........................................................................... 159

Fig. 8.10 Placement Pattern of CPUs Around the Pillars ............................... 160

Fig. 8.11 An Example of the CPU Placement Algorithm .............................. 160

xvi

BookID 186671_ChapID FM1_Proof# 1 - 28/08/2009 BookID 186671_ChapID FM1_Proof# 1 - 28/08/2009

List of Figures

Fig. 8.12 Intra-Layer and Inter-Layer Data Migration in the 3D L2

Architecture ..................................................................................... 163

Fig. 8.13 Average L2 Hit Latency Values Under Different Schemes............. 166

Fig. 8.14 Number of Block Migrations for CMP-DNUCA

and CMP-DNUCA-3D, Normalized With Respect

to CMP-DNUCA-2D ...................................................................... 167

Fig. 8.15 IPC Values Under Different Schemes ............................................. 167

Fig. 8.16 Average L2 Hit Latency Values Under Different Schemes............. 168

Fig. 8.17 Impact of the Number of Pillars (CMP-DNUCA-3D Scheme) ...... 168

Fig. 8.18

Impact of the Number of Layers (CMP-SNUCA-3D Scheme) .......................

169

Fig. 9.1

The Evolution from a Hop-By-Hop 3D Structure

to a True 3D Crossbar ......................................................................................

172

Fig. 9.2

Face-to-Back (F2B) Bonding and the Assumed Vertical

Via Layout in Chapter 9 ...................................................................................

174

Fig. 9.3

A 3D Symmetric NoC Network .......................................................................

177

Fig. 9.4

A 3D NoC-Bus Hybrid Architecture ...............................................................

178

Fig. 9.5

Side View of the Inter-Layer Via Structure in a 3D NoC-Bus

Hybrid Structure ...............................................................................................

178

Fig. 9.6

NoC Routers with True 3D Crossbars .............................................................

179

Fig. 9.7

Side View of the Inter-Layer Via Structure in a 3D Crossbar ..........................

180

Fig. 9.8

A 3D 3x3x3 Crossbar in Conceptual Form ......................................................

181

Fig. 9.9

Different NoC Router Switching Mechanisms ................................................

183

Fig. 9.10

Overview of the 3D DimDe NoC Architecture ................................................

184

Fig. 9.11

Vertical (Inter-Layer) Link Arbitration Details ................................................

185

Fig. 9.12

An Example of a Non-XYZ Routing Algorithm .............................................

186

Fig. 9.13

Architectural Detail of the Proposed 3D DimDe NoC Router.........................

188

Fig. 9.14

Virtual Channel Assignments in the Vertical

Module of DimDe ............................................................................................

189

Fig. 9.15

Thermal Effects on Inter-Layer Propagation Delay .........................................

189

Fig. 9.16

Impact of the Number of Vertical Bundles on Performance ............................

192

Fig. 9.17

Average Latency with various Synthetic Trafﬁc Patterns

(XYZ Routing) .................................................................................................

194

Fig. 9.18

Throughput with various Synthetic Trafﬁc Patterns

(XYZ Routing) .................................................................................................

195

Fig. 9.19

Average Latency with various Commercial and Scientiﬁc

Workloads ........................................................................................................

195

Fig. 9.20

Energy-Delay Product (EDP) with various Commercial

and Scientiﬁc Workloads..................................................................................

196

Fig. 10.1

Reduction in the Number of Routers When Using

the MEP Topology ...........................................................................................

200

Fig. 10.2

Overview of the Fast Path Architecture ...........................................................

202

Fig. 10.3

Cache Compression (CC) vs. NoC Compression (NC) ...................................

204

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片上网络（Network-on-Chip）：架构与路由器算法

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