IEEE 1687-2004：半导体设备内嵌仪表访问与控制标准

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IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device (IEEE 1687) 是由IEEE Test Technology Standards Committee 赞助并制定的一份针对嵌入在半导体器件中的仪器访问与控制的标准规范。这份标准主要适用于系统级芯片（System-on-Chip, SOC）领域，特别是用于设计和实施数字故障检测（Digital Fault Tolerance, DFT）控制总线的场景。该标准的主要目标是提供一种方法，允许开发者在不具体定义仪器或其功能细节的情况下，通过 IEEE 1149.1™ 测试访问端口 (TAP) 或其他信号，访问嵌入在芯片内部的仪器。这种方法旨在促进模块化测试和调试，提高芯片设计的灵活性，并简化对复杂集成电路中众多子系统的诊断和维护。 IEEE Std 1687-2014 版本于2014年11月3日获得IEEE-SA Standards Board 的批准，表明它已经经过了标准化组织的严格审查和认可。这一版本对于像Mobile Peak Holdings Ltd. 这样的授权用户来说，具有有限的使用权，仅能在特定的时间和地点（2016年3月15日07:27:10 UTC，从IEEE Explore下载）访问，且可能存在使用限制。标准定义了一套通用的接口和协议，使得测试工具可以与各种嵌入式仪器进行通信，而无需深入理解每个仪器的具体实现。这对于大规模集成电路生产环境中的测试自动化至关重要，因为它减少了定制化测试代码的需求，并提高了整个测试流程的效率。此外，IEEE 1687还强调了安全性考量，确保数据交换的可靠性和隔离性，以防止未经授权的访问或干扰。通过遵循这个标准，设计者可以确保他们的产品符合行业最佳实践，同时满足日益增长的对电子设备安全性和可测试性的需求。 IEEE 1687标准是半导体行业的一个重要里程碑，它规范了嵌入式仪器的访问和控制，推动了测试技术的发展，提高了集成电路的可测试性和整体性能。任何从事SOC设计、验证或测试的工程师都应熟知和遵循此标准，以确保产品的质量和市场竞争力。

IEEE Std 1687-2014

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

1.3 Background

There exists the widespread use of embedded instrumentation [such as built-in self-test (BIST) engines,

complex I/O characterization and calibration, embedded timing instrumentation, etc.), each of which is

accessed and managed by a variety of external controllers using a variety of mechanisms and protocols.

Therefore, a need exists for standardization of these methods in order to facilitate an efficient and orderly

process for the preparation of tests that access and control these embedded instruments. Given the

widespread use of IEEE 1149.1 TAP and boundary-scan architecture as a gateway to many internal test,

debug, and programming features, it is logical to build upon the foundation of the boundary scan standards

(IEEE Std 1149.1-1990 [B2], IEEE Std 1149.1-2001, IEEE Std 1149.1-2013 , IEEE Std 1149.4™-2010

[B3], IEEE Std 1149.6™-2010 [B4], IEEE Std 1532™-2002 [B5], and IEEE Std 1500™-2005) to support

TAP-based access to internal device test features in a standardized manner.

IEEE Std 1149.1-2013

extended previous versions of that standard to include procedural access to reconfigurable test data

registers (TDRs) accessible via the TAP. IEEE Std 1687 describes an instrument-centric approach to this

problem that allows retargeting from instrument ports through a wide variety of on-chip network

configurations (of which IEEE Std 1500 is one example) to a device interface (of which the TAP is one

example). Like IEEE Std 1500, IEEE Std 1687 specifies how to build a conformant on-chip network while

not forcing a specific device interface to the network. IEEE Std 1687 has taken a more descriptive than

prescriptive approach for specifying the on-chip network, thus allowing many existing architectures to

conform.

This standardization effort is intended to address the access to on-chip instrumentation, not the instruments

themselves. The elements of standardized access include the following:

a) The hardware architecture for connecting instruments to the TAP via a serial access network and/or

to other interfaces via a serial or parallel access network,

b) A hardware description language (HDL) that documents this access network between the

instruments and device interfaces, and

c) A procedure description language that documents the operation of the instruments.

Items that have been specifically included in the scope of the standard include the application of

instrument-level procedures retargeted through various levels of hierarchy, the retargeting of intellectual

property (IP)-level patterns to device-level TAP patterns, and the documentation of the connection of

instruments to other (non-TAP) interfaces.

Items that have been excluded from the scope of the standard are the detailed off-chip protocols for

instrument communication over non-TAP interfaces, synchronized interoperation between instruments, and

the assurance of reusability of chip-level patterns at board or system levels.

The goal of IEEE Std 1687 is to facilitate the use and reuse of internal instrumentation by providing a

standard yet flexible network architecture for accessing the instruments and standard descriptions of both

the network and the operation of the instruments. Given the considerable number of devices containing

internal instruments that are already available, this standard has made every reasonable attempt to provide

support for the description of commonly used legacy implementations. The standard also supports forward-

looking architectures that are scalable and uniform in their approach to accessing embedded instruments in

a hierarchical manner.

1.4 Organization

This standard is organized as follows:

The numbers in brackets correspond to those of the bibliography in Annex G.

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IEEE Std 1687-2014

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

Clause 1 provides background and context for this standard.

Clause 2 provides references necessary to understand this standard.

Clause 3 defines the terminology and nomenclature used in this standard.

Clause 4 is a tutorial that outlines the technologies addressed and utilized by this standard. This clause does

not contain rules.

Clause 5 provides rules for the network architecture used by this standard.

Clause 6 provides rules for documenting the hardware architecture used by this standard.

Clause 7 provides rules for documenting the operation of the instruments used by this standard.

Clause 8 provides rules for manipulating the data produced by the instruments and for using Tcl as a

programming language to manage instrument interactions.

Annex A (informative) specifies the language constructs used to describe the access network.

Annex B (informative) specifies the basic language constructs used to interact with the instruments.

Annex C (informative) specifies the advanced (Tcl) language constructs used to interact with the

instruments.

Annex D (informative) identifies the subtle differences between the otherwise mostly common

implementation of PDL.

Annex E (informative) presents many use cases showing applications of ICL and PDL to common circuits.

Annex F (informative) discusses practical issues for the implementation of commonly used circuits.

Annex G (informative) is a bibliography.

1.5 Context

The context in which this standard is applicable is illustrated in Figure 1, which shows a device under test

(DUT) that includes a TAP interface, some pins and an I/O interface, and three (lightly shaded) access

networks through which those interfaces are connected to four internal instruments. This standard defines

the architecture of and a structured way to describe the hardware contents of the access network and the

well-defined interfaces (darker shaded small rectangles) between the access networks and the instruments.

This standard also describes the software content (e.g., test patterns and procedures) that is delivered over

the access network to interact with the instruments.

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IEEE Std 1687-2014

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

DUT

TAP

I/O interface

Instrument 2

Instrument 3

Instrument 4

Access

network

Access

network

Access

network

Instrument 1

Figure 1 —IEEE 1687 context

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture.

IEEE Std 1149.1-2013, IEEE Standard Test Access Port and Boundary-Scan Architecture.

IEEE Std 1500, IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits.

3. Definitions, acronyms, and abbreviations

3.1 Definitions

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online should be consulted for terms not defined in this clause.

access network: See: network.

AccessLink: An Instrument Connectivity Language (ICL) keyword that is used to describe the details of

the interface between the device pins and the network. The IEEE 1149.1 test access port (TAP) has a

well-defined description built into ICL.

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers, Inc.

IEEE Standards Dictionary Online subscription is available at:

http://www.ieee.org/portal/innovate/products/standard/standards_dictionary.html

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IEEE Std 1687-2014

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

active scan chain (or Active shift path): A set of serially connected shift register bits that advance by one

bit per test clock cycle when enabled to shift. The network in the module (or modules) containing the

segments of the scan chain is required to be selected in order to allow activity on the shift enable control

signal.

Alias: An Instrument Connectivity Language (ICL) keyword that assigns a name to a given group of

ICL objects (register bits or ports), which are then allowed to be referred to collectively by that name.

black-box module: A module description in Instrument Connectivity Language (ICL) that has only

ports, but no contents. These modules may be used to hide proprietary intellectual property (IP). Such

modules are often used in conjunction with iScan commands in Procedural Description Language (PDL)

and thus have a precisely defined length at any given time, which is associated with each ScanInterface of

the black-box module.

NOTE—See 6.4.5 and 7.3.5 for details.

boundary-scan testing: Testing of board or backplane interconnections between device pins as supported

by IEEE Std 1149.1, IEEE Std 1149.4, and IEEE Std 1149.6. This testing technology is intended to find

manufacturing defects such as open solder joints, shorted signal traces, broken bond wires, damaged drivers

and receivers, etc.

built-in self-test (BIST), built-in test (BIT): Test of a component of a system by itself; more specifically,

by test circuitry added to the mission circuitry that causes the component to exercise itself and report the

results with no or minimal interaction with external sources. BIST may be applied on embedded

components of a chip (such as memories, analog blocks, or I/O interfaces), on entire chips, or on entire

boards or systems.

capture-shift-update (CSU): The sequence of operations applied to a test data register (TDR) to capture

new data from the data-input port, shift the data through the TDR, then update the newly shifted data into

the update stage of the TDR.

care bit: A port or register that has a non-X value that must be present in order to satisfy an objective (such

as enabling a scan chain or maintaining a previously written value).

client interface: The port functions that attach a module to a host interface in a network. A client

interface consumes control signals from the host interface and exchanges data with it.

client module: The successor of a module in a network organized in a host-client fashion. A host

module’s client is closer to the instrument. A client module contains a client interface that connects to a

host interface. Contrast: host module.

component: A hardware entity that is one of the primitive building blocks of the network, including

storage elements, multiplexers, and logic.

controlling state: A representation in a software model of the set of logic values that have been written to

ports and/or storage elements in the network.

NOTE—See description in 7.3.3.

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IEEE Std 1687-2014

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

core: A component of a device that may appear multiple times or may be reused in other devices. Also

referred to as an IP (intellectual property) core or simply as IP.

data register: A set of one or more storage cells with a parallel input and a parallel output.

device: A collection of circuitry with a well-defined test boundary, generally including a TAP and physical

pins.

device interface: The circuitry that connects the device pins to the instrument access network. A TAP

controller is the most common example of a device interface for an instrument access network, but other

interfaces (I

C, a parallel microprocessor bus, a PCI-express port, etc.) could also serve as device interfaces

if correctly adapted to the instrument access network. The device interface itself is not considered part of

the network.

embedded test access port (eTAP): A captive version of a TAP thatthat acts as the interface to a portion

of the network or a wrapped instrument rather than serving as the device-level TAP. An embedded TAP is

typically accompanied by an embedded TAP controller (eTAPC).

embedded test access port controller (eTAPC): A finite state machine largely corresponding to that

specified in IEEE Std 1149.1, which responds to the embedded TAP signals used as the interface to a sub-

network or instrument. To force synchronization, there is a slight restriction from the IEEE 1149.1 TAP

controller state diagram with respect to the arc traversed when the eTAPC is being re-selected.

NOTE—See 5.14.4.

expected state: A representation in a software model of the set of logic values that have been read from

ports and/or storage elements in the network.

NOTE—See description in 7.3.3.

fan-in: The set of primitive elements encountered by tracing backwards through the network from the

inputs of a specific element.

global reset: A signal that places all modules into their specified reset states.

handoff module: A module that is intended to be exchanged between parties [intellectual property (IP)

providers and integrators] or tools (e.g., simulators or rule checkers) for which all access network ports

must be declared and must match. A common example: a wrapped instrument delivered by an IP provider

must have all the ports of the Instrument Connectivity Language (ICL) module present in the associated

to the access network; these need not be declared in the ICL module.

hardware description language (HDL): Any of a number of languages that describe the structural

components, connectivity, behavior, or combinations thereof, of a circuit, including Verilog

, VHDL,

Instrument Connectivity Language (ICL), etc.

NOTE—Verilog is a registered trademark of Cadence Design Systems, Inc.

host interface: The port functions that attach a module to a client interface. A host interface provides

control signals to a client interface and exchanges data with it.

host module: The predecessor of a module in a network organized in a host-client fashion. A client

module’s host is closer to the device interface. A Host Module contains a host interface to which a client

interface connects. Contrast: client module.

IEEE 1687 network: See: network.

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