"Elpida HM5117805LJ-6 DDR3 中文数据手册及产品介绍"

需积分: 9 108 浏览量更新于2023-12-24 5 收藏 539KB PDF 举报

The Elpida-HM5117805LJ-6 is a DDR3 SDRAM module that is designed for high performance and low power consumption. It is a 16 M EDO DRAM with 2-Mword × 8-bit organization and 2 k refresh. This module employs the most advanced CMOS technology and offers Extended Data Out (EDO) Page Mode for high speed access. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. The HM5117805 Series was released on Jun. 27, 2001, and is now an End-of-Life (EOL) product. This module is designed for use in applications that require high performance and low power consumption. The HM5117805 is a CMOS dynamic RAM organized as 2,097,152-word × 8-bit. It offers Extended Data Out (EDO) Page Mode as a high-speed access. This module is suitable for use in applications that require high performance and low power consumption. It employs the most advanced CMOS technology to deliver high performance and low power consumption. In summary, the Elpida-HM5117805LJ-6 is a DDR3 SDRAM module designed for high performance and low power consumption. It employs advanced CMOS technology and offers Extended Data Out (EDO) Page Mode for high-speed access. As an End-of-Life (EOL) product, it is suitable for use in applications that require high performance and low power consumption.

EOL Product

HM5117805 Series

Data Sheet E0156H10

DC Characteristics (Ta = 0 to +70°C, V

= 5 V ± 10%, V

= 0 V)

HM5117805

-5 -6 -7

Parameter Symbol Min Max Min Max Min Max Unit Test conditions

Operating current*

CC1

— 110 — 100 — 90 mA t

= min

Standby current I

CC2

— 2 — 2 — 2 mA TTL interface

RAS, CAS = V

Dout = High-Z

— 1 — 1 — 1 mA CMOS interface

RAS, CAS ≥ V

– 0.2 V

Dout = High-Z

Standby current

(L-version)

CC2

— 150 — 150 — 150 µA CMOS interface

RAS, CAS ≥ V

– 0.2 V

Dout = High-Z

RAS-only refresh current*

CC3

— 110 — 100 — 90 mA t

= min

Standby current*

CC5

—5 —5 —5 mA RAS = V

CAS = V

Dout = enable

CAS-before-RAS refresh

current

CC6

— 110 — 100 — 90 mA t

= min

EDO page mode

current*

CC7

— 100 — 90 — 85 mA t

HPC

= min

Battery backup current*

(Standby with CBR refresh)

(L-version)

CC10

— 500 — 500 — 500 µA CMOS interface

Dout = High-Z

CBR refresh:

= 62.5 µs

RAS

≤ 0.3 µs

Self refresh mode current

(L-version)

CC11

— 300 — 300 — 300 µA CMOS interface

RAS, CAS ≤ 0.2V

Dout = High-Z

Input leakage current I

–10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V

Output leakage current I

–10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V

Dout = disable

Output high voltage V

2.4 V

V High Iout = –2 mA

Output low voltage V

0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA

Notes: 1. I

depends on output load condition when the device is selected. I

max is specified at the output

open condition.

2. Address can be changed once or less while RAS = V

3. Address can be changed once or less while CAS = V

4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V).

剩余31页未读，继续阅读

不觉明了

粉丝: 3514
资源: 5759

"Elpida HM5117805LJ-6 DDR3 中文数据手册及产品介绍"

ddr3中文数据手册Elpida Memory-HM5117805LJ-5

ddr3中文数据手册Elpida Memory-HM5117805

ddr3中文数据手册Elpida-HM5164165FJ-5

ELPIDA 维哈文输入法

ELPIDA_HOW_TO_USE_DDR2 _SDRAM.pdf

A20 DDR3 支持列表

DDR-Ⅱ与DDR-Ⅲ（一）高手进阶，终极内存技术指南——完整进阶版 .doc

维文输入法

【水果识别】基于matlab GUI形态学水果大小识别【含Matlab源码 920期】.md

【瑕疵检测】基于matlab瓶盖瑕疵检测【含Matlab源码 730期】.md

最新资源