Nanya DDR3内存规格详解

DDR3规格

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"DDR3规格说明书是Nanya公司针对其NT5CB(C)256M8IN/NT5CB(C)128M16INP两种内存芯片制定的技术规范，详细阐述了这些DDR3内存的特性、功能和操作模式，以确保与JEDEC DDR3标准兼容。" DDR3内存，全称为DDR3 SDRAM（Double Data Rate Third Generation Synchronous Dynamic Random-Access Memory），是一种高速同步动态随机存取内存，具有以下主要特点： 1. **JEDEC DDR3合规性**：遵循JEDEC制定的DDR3标准，确保了与其他DDR3设备的兼容性。 2. **8n预取架构**：DDR3内存采用8n预取技术，意味着数据总线在每个时钟周期内处理8位数据，提高了数据传输效率。 3. **差分时钟与数据 strobe**：使用差分时钟信号CK/CK#和数据 strobe DQS/DQS#，增强了信号的抗干扰能力，提高了数据传输的准确性。 4. **双数据速率**：在DQ和DQS线上实现双倍数据速率，即数据在上升沿和下降沿都被读取或写入。 5. **数据完整性**：通过DRAM内置的温度感应器（TS）支持自动自刷新（ASR）功能，以及自动刷新和自刷新模式，确保数据在不同环境下的稳定性。 6. **节能模式**：支持部分阵列自刷新（PASR）、电源关闭模式，以及多种低功耗模式，以适应不同应用场景的需求。 7. **CAS延迟**：提供多种CAS（Column Address Strobe）延迟选项，如6、7、8、9、10、11、13、14，以适应不同的系统性能需求。 8. **CAS写入延迟**：包括5、6、7、8、9、10等不同级别的CAS写入延迟，优化写入操作的响应时间。 9. **附加延迟**：可设置为0、CL-1或CL-2，进一步调整内存访问速度。 10. **写恢复时间**：支持5、6、7、8、10、12、14、16等不同级别的写恢复时间，确保写操作的正确完成。 11. **突发类型**：支持顺序和交错两种突发类型，提高数据访问的灵活性。 12. **突发长度**：支持BL8（8个数据单元）和BC4（4个数据单元），并可以在运行时动态切换到BC4或8。 13. **可编程功能**：包括自刷新温度范围（正常或扩展）、输出驱动阻抗（34/40欧姆）、片上终结电阻（Rtt_Nom和Rtt_WR）的配置，以及预充电源关闭速度（慢速或快速）等，允许根据系统需求进行定制。 14. **信号完整性**：配置可变的数据选择（DS）以适应系统兼容性，可配置的片上终结（ODT）确保信号质量，通过外部ZQ引脚进行ZQ校准，以精确控制DS/ODT阻抗。这份规格说明书详细描述了Nanya DDR3内存芯片的各个方面，对于系统设计师和硬件工程师来说，是理解和使用这些内存芯片的重要参考。

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DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

Version 1.5 16 Nanya Technology Cooperation ©

MOD

Timing

CKE

MRS NOP NOP NOP NOPCMD

ADDR

tMOD

Non

MRS

VAL

Old Setting

Updating Setting

New Setting

VAL

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

Version 1.5 18 Nanya Technology Cooperation ©

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

command via A12/.

Burst Type and Burst Order

Burst

Length

Read

Write

Starting

Column

Address

(A2,A1,A0)

Burst type:

Sequential

(decimal)

A3 = 0

Burst type:

Interleaved

(decimal)

A3 = 1

Note

Chop

Read

0,0,0

0,1,2,3,T,T,T,T

1,2,3

0,0,1

1,2,3,0,T,T,T,T

1,0,3,2,T,T,T,T

0,1,0

2,3,0,1,T,T,T,T

0,1,1

3,0,1,2,T,T,T,T

3,2,1,0,T,T,T,T

1,0,0

4,5,6,7,T,T,T,T

1,0,1

5,6,7,4,T,T,T,T

5,4,7,6,T,T,T,T

1,1,0

6,7,4,5,T,T,T,T

1,1,1

7,4,5,6,T,T,T,T

7,6,5,4,T,T,T,T

Write

0,V,V

0,1,2,3,X,X,X,X

1,2,4,5

1,V,V

4,5,6,7,X,X,X,X

Read

0,0,0

0,1,2,3,4,5,6,7

0,0,1

1,2,3,0,5,6,7,4

1,0,3,2,5,4,7,6

0,1,0

2,3,0,1,6,7,4,5

0,1,1

3,0,1,2,7,4,5,6

3,2,1,0,7,6,5,4

1,0,0

4,5,6,7,0,1,2,3

1,0,1

5,6,7,4,1,2,3,0

5,4,7,6,1,0,3,2

1,1,0

6,7,4,5,2,3,0,1

1,1,1

7,4,5,6,3,0,1,2

7,6,5,4,3,2,1,0

Write

V,V,V

0,1,2,3,4,5,6,7

2,4

Note:

1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8

mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected

on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that

during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.

3. T: Output driver for data and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

5. X: Do not Care.

DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

CAS Latency

The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in

clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does

not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency

(CL); RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM

manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.

Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK

must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous

operations.)

Write Recovery

The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)

and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be

equal or larger than tWR (min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

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