LMH1983
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SNLS309I –APRIL 2010–REVISED DECEMBER 2014
8 Detailed Description
8.1 Overview
The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a
variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The
LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with
programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-
stage PLL architecture. The first stage is a VCXO-based PLL (PLL1) that requires an external 27 MHz VCXO
and loop filter. In Genlock mode, PLL1 can phase lock a low loop bandwidth VCXO clock to the input reference.
The VCXO provides a low phase noise clock source to attenuate input timing jitter for minimum jitter transfer.
The combination of the external VCXO, external loop filter, and programmable PLL parameters provide flexibility
for the system designer to optimize the loop bandwidth and loop response for the application.
The second stage consists of three PLLs (PLL2, PLL3, PLL4) with integrated VCOs and loop filters. These PLLs
continually track the reference VCXO clock phase from PLL1 regardless of the device mode. The PLL2 and PLL3
have pre-configured divider ratios to provide frequency multiplication or translation from the VCXO clock
frequency to generate the two common HD clock rates (148.5 MHz and 148.35 MHz). PLL4 is pre-configured to
generate an audio clock that defaults to a 24.576 MHz output, although PLL4 has several registers that allow it to
be re-configured for a variety of applications.
The VCO PLLs use a high loop bandwidth to assure PLL stability, so the VCXO of PLL1 must provide a stable
low-jitter clock reference to ensure optimal output jitter performance. Any unused clock or TOF output can be
placed in Hi-Z mode. This may be useful for reducing power dissipation as well as reducing jitter or phase noise
on the active clock output. The TOF pulse can be programmed to indicate the start (top) of frame and even
provide format cross-locking. The output format registers should be programmed to specify the output timing
(output clocks and TOF pulse), the output timing offset relative to the reference, and the output initialization
(alignment) to the reference frame.
When a loss of reference occurs during genlock, PLL1 can default to either Free-run or Holdover operation.
When Free-run is selected, the output frequency accuracy will be determined by the external bias on the free-run
control voltage input pin, VC_LPF. When Holdover is selected, the loop filter can hold the control voltage to
maintain short-term output phase accuracy for a brief period in order to allow the application to select the
secondary input reference and re-lock the outputs. These options in combination with a proper PLL1 loop
response design can provide flexibility to manage output clock behavior during loss and re-acquisition of the
reference. The reference status and PLL lock status flags can provide real-time status indication to the
application system. The loss of reference and lock detection thresholds can also be configured.
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