"TLIN2021A-Q1.pdf：符合汽车应用标准的故障保护 LIN 收发器"

158 浏览量更新于2023-12-21 4 收藏 1.97MB PDF 举报

TI-TLIN2021A-Q1.pdf; Lin transceiver; TLIN2021A-Q1 fault-protected LIN transceiver, equipped with suppression and wake-up functions TLIN2021A-Q1 is a fault-protected LIN transceiver designed for automotive applications. It is compliant with the AEC-Q100 (Grade 1) standard and is also compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, and ISO 17987-4 electrical physical layer (EPL) specifications. Additionally, it meets the SAE J2602-1 LIN network standard for automotive applications. The transceiver provides features such as functional safety documentation to assist with the design of functional safety systems. It supports both 12V and 24V applications and has a wide operating input voltage range of 4.5V to 45V. The LIN transmission data rate can reach up to 20kbps, and the LIN reception data rate can reach up to 100kbps. It operates in normal, standby, and sleep modes. One of the key features of TLIN2021A-Q1 is its low power mode wake-up support, which can be achieved through remote wake-up via the LIN bus, local wake-up via the WAKE pin, or local wake-up via the EN pin. The transceiver also integrates a 45kΩ LIN pull-up resistor and utilizes the INH pin to control system-level power consumption. In terms of protection features, TLIN2021A-Q1 offers ±60V LIN bus fault tolerance, 58V load dump support, under-voltage protection on VSUP, TXD dominant state timeout, thermal shutdown, and protection against system-level undervoltage node or ground disconnect failures. Overall, the TLIN2021A-Q1 transceiver is a robust and reliable solution for automotive LIN communication, providing a wide range of features and protection mechanisms to ensure safe and efficient operation in vehicle networks. Its compliance with industry standards and support for functional safety make it an ideal choice for automotive LIN applications.

7.7 Electrical Characteristics (continued)

parameters valid across -40℃ ≤ T

≤ 150℃ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BUS_NO_BAT

Leakage current, loss of supply

SUP

= GND

0 V ≤ V

LIN

≤ 36 V

5 µA

RSLEEP

Pull-up current source to V

SUP

sleep mode V

SUP

= 27 V, LIN = GND

–20 –1.5

µA

Pull-up resistor to V

SUP

Normal and standby modes 20 45 60

kΩ

LIN

Capacitance of the LIN pin V

SUP

= 14 V 25 pF

INH Output Terminal

ΔV

High level voltage drop INH with respect to V

SUP

INH

= - 0.5 mA 0.5 1 V

LKG(INH)

Leakage current sleep mode INH = 0 V

–0.5

0.5 µA

WAKE Input Terminal

High-level input voltage Standby and sleep mode

SUP

–

1.8

Low-level input voltage Standby and sleep mode

SUP

–

3.85

High-level input leakage current WAKE = V

SUP

- 1 V

–25 –12.5

µA

Ligh-level input leakage current WAKE = 1 V 15 25 µA

WAKE

WAKE hold time Wake up time from sleep mode 5 50 µs

Duty Cycle Characteristics

12V

Duty cycle 1

(3)

ISO 17987 Param 27

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

= 7 V to 18 V, t

BIT

= 50 µs

D1 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.396

12V

Duty cycle 1

(3)

(6)

REC(MAX)

= 0.665 x V

SUP

DOM(MAX)

= 0.499 x V

SUP

= 4.5 V to 7 V, t

BIT

= 50 µs

D1 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.396

12V

Duty cycle 1

(1)

(2)

(6)

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

= 7 V to 18 V, t

BIT

= 52 µs

D1 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.396

12V

Duty cycle 2

(3)

ISO 17987 Param 28

REC(MIN)

= 0.422 x V

SUP

DOM(MIN)

= 0.284 x V

SUP

= 7 V to 18 V, t

BIT

= 50 µs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.581

12V

Duty cycle 2

(3)

(6)

REC(MIN)

= 0.496 x V

SUP

DOM(MIN)

= 0.361 x V

SUP

= 4.5 V to 7 V, t

BIT

= 50 µs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.581

12V

Duty cycle 2

(1)

(2)

(6)

REC(MIN)

= 0.422 x V

SUP

DOM(MIN)

= 0.284 x V

SUP

= 7 V to 18 V, t

BIT

= 52 µs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.581

12V

Duty cycle 3

(3)

ISO 17987 Param 29

REC(MAX)

= 0.778 x V

SUP

DOM(MAX)

= 0.616 x V

SUP

= 7 V to 18 V, t

BIT

= 96 µs

D3 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.417

12V

Duty cycle 3

(3)

(6)

REC(MAX)

= 0.665 x V

SUP

DOM(MAX)

= 0.499 x V

SUP

= 4.5 V to 7 V, t

BIT

= 96 µs

D3 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.417

TLIN2021A-Q1

ZHCSMB3 – MARCH 2021

www.ti.com.cn

8 Submit Document Feedback

Product Folder Links: TLIN2021A-Q1

7.7 Electrical Characteristics (continued)

parameters valid across -40℃ ≤ T

≤ 150℃ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

12V

Duty cycle 3

(1)

(2)

(6)

REC(MAX)

= 0.778 x V

SUP

DOM(MAX)

= 0.616 x V

SUP

= 7 V to 18 V, t

BIT

= 96 µs

D3 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.417

12V

Duty cycle 4

(3)

ISO 17987 Param 30

REC(MIN)

= 0.389 x V

SUP

DOM(MIN)

= 0.251 x V

SUP

= 7 V to 18 V, t

BIT

= 96 µs

D4 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.59

12V

Duty cycle 4

(3)

(6)

REC(MAX)

= 0.496 x V

SUP

DOM(MAX)

= 0.361 x V

SUP

= 4.5 V to 7 V, t

BIT

= 96 µs

D4 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.59

12V

Duty cycle 4

(1)

(2)

(6)

REC(MIN)

= 0.389 x V

SUP

DOM(MIN)

= 0.251 x V

SUP

= 7 V to 18 V, t

BIT

= 96 µs

D4 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.59

24V

Duty cycle 1

ISO 17987 Param 72

REC(MAX)

= 0.710 x V

SUP

DOM(MAX)

= 0.554 x V

SUP

= 15 V to 36 V, t

BIT

= 50 µs

D1 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.330

24V

Duty cycle 2

ISO 17987 Param 73

REC(MIN)

= 0.446 x V

SUP

DOM(MIN)

= 0.302 x V

SUP

= 15.6 V to 36 V, t

BIT

= 50 µs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.642

24V

Duty cycle 3

ISO 17987 Param 74

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

= 7 V to 36 V, t

BIT

= 96 µs

D3 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.386

24V

Duty cycle 3

(6)

REC(MAX)

= 0.645 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

= 4.5 V to 7 V, t

BIT

= 96 µs

D3 = t

BUS_rec(min)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.386

24V

Duty cycle 2

(6)

ISO 17987 Param 75

REC(MIN)

= 0.422 x V

SUP

DOM(MIN)

= 0.284 x V

SUP

= 4.5 V to 36 V, t

BIT

= 96 µs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

)

See Figure 8-8 and Figure 8-9

0.591

Duty cycle 1 at low battery

(1)

(2)

(6)

REC(MAX)

= 0.665 x V

SUP

DOM(MAX)

= 0.499 x V

SUP

= 5.5 V to 7 V, t

BIT

= 52 µs

0.396

Duty cycle 2 at low battery

(1)

(2)

(6)

REC(MAX)

= 0.496 x V

SUP

DOM(MAX)

= 0.361 x V

SUP

= 6.1 V to 7 V, t

BIT

= 52 µs

0.581

Duty cycle 3 at low battery

(1)

(2)

(6)

REC(MAX)

= 0.665 x V

SUP

DOM(MAX)

= 0.499 x V

SUP

= 5.5 V to 7 V, t

BIT

= 96 µs

0.396

4LB

Duty cycle 4 at low battery

(1)

(2)

(6)

REC(MAX)

= 0.496 x V

SUP

DOM(MAX)

= 0.361 x V

SUP

= 6.1 V to 7 V, t

BIT

= 96 µs

0.581

r-d max_D1

Transmitter propagation delay timings for the duty

cycle

(1)

(2)

(6)

Recessive to dominant

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

7 V ≤ V

SUP

≤ 18 V, t

BIT

= 52 µs

REC(MAX)_D1

- t

DOM(MIN)_D1

10.8 µs

d-r max_D2

Transmitter propagation delay timings for the duty

cycle

(1)

(2)

(6)

Dominant to recessive

REC(MAX)

= 0.422 x V

SUP

DOM(MAX)

= 0.284 x V

SUP

7 V ≤ V

SUP

≤ 18 V, t

BIT

= 52 µs

DOM(MAX)_D2

- t

REC(MIN)_D2

8.4 µs

www.ti.com.cn

TLIN2021A-Q1

ZHCSMB3 – MARCH 2021

Submit Document Feedback

Product Folder Links: TLIN2021A-Q1

剩余40页未读，继续阅读

不觉明了

粉丝: 3800
资源: 5759

"TLIN2021A-Q1.pdf：符合汽车应用标准的故障保护 LIN 收发器"

TI-TLIN2021-Q1.pdf

TI-TLIN1021A-Q1.pdf

TI-TLIN1022A-Q1.pdf

TI-TLIN2024A-Q1.pdf

TI-TLIN1024A-Q1.pdf

TI-TLIN1029A-Q1.pdf

TI-TLIN2029A-Q1.pdf

TI-TLIN2022A-Q1.pdf

TI-TLIN1024-Q1.pdf

TI-TLIN1021-Q1.pdf

最新资源