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STM32 series/value lines Flash memory page sizes
Single bank mode
support
Dual bank mode
support
STM32U5 series 8 Kbytes (512 words of 128 bits) Yes Yes
STM32C0x1 2 Kbytes (256 words of 64 bits) Yes No
STM32H5 series 8 Kbytes (512 words of 128 bits) Yes Yes
STM32H5 series using high-cycle
data area
(2)
6 Kbytes (3072 words of 16 bits) Yes Yes
1. When in single bank mode, these devices operate 128 bits wide read accesses. However, the EEPROM emulation solution
is designed for 64 bits wide read accesses.
2. The high-cycle data area is available on the STM32H563/H573 and the STM32H562 MCUs.
The minimal write width in flash memory is 64 bits (128 bits for STM32U5 and STM32H5 series, or 16 bits for
STM32H5 series using high-cycle data area) due to its ECC (error correcting code) that cannot be switched off.
Only zeros (0x0000 0000 0000 0000, or 0X0000 0000 0000 0000 0000 0000 0000 0000 for STM32U5 series) can
be written to an already programmed nonnull flash memory line. As the first four words are used by the header, a
flash memory page can store up to 252 variable elements when the page size is 2 Kbytes, and up to 508 variable
elements when the page size is 4 Kbytes.
The possible states of a flash memory page are coded by writing 0xAAAA AAAA AAAA AAAA (or 0xAAAA AAAA
AAAA AAAA AAAA AAAA AAAA AAAA for the STM32U5 series) into the page header. It is possible to determine
the page state using the following procedure:
• The page is in the ERASING state if its fourth line is not erased.
• The page is in the VALID state if the third line is not erased and the fourth line is erased.
• The page is in the ACTIVE state if the second line is not erased and the third and fourth.
• The page is in the ACTIVE state if the second line is not erased and the third and fourth lines are erased.
• The page is in the RECEIVE state if the first line is not erased and the second, third, and fourth lines are
erased.
• The page is in the ERASED state if the first four lines are erased.
This algorithm allows the coding of all states and transitions described in Section 3.2: Page status valid
transitions. Each variable element is defined by a virtual address and a data value to be stored in flash memory
for subsequent retrieval or update. In the implemented software, the virtual address is 16 bits long and the data
value is either 8 bits, 16 bits, or 32 bits long. The driver requires the virtual address values to be between 0x0001
(0x0000 corresponds to an EEPROM element invalidated by the driver), and the maximum number of EEPROM
variables required. Also, since virtual addresses are 16-bits wide, the maximum number of EEPROM variables
cannot exceed 0xFFFE (0xFFFF corresponds to an erased flash memory line). Moreover, the number of variables
is limited by the size of the product flash memory (see Section 4.6: Computing the required size of flash memory
for EEPROM emulation).
Each element also contains a 16-bit CRC that is used to check the element integrity. When data is modified, the
modified data associated with the same virtual address is stored in a new flash memory location. Data retrieval
returns the up-to-date data value.
AN4894
Implementing EEPROM emulation
AN4894 - Rev 9
page 7/31