AX88180
9
ASIX ELECTRONICS CORPORATION
Asynchronous signal CRS is asserted by the PHY when either the transmitted or
receive medium is non-idle.
MDIO IO2, PU,
8mA
59 Station Management Data Input /Output:
Serial data input/Output transfers from/to the PHY. The transfer protocol conforms
to the IEEE 802.3u MII specification.
MDC O2, 8mA 58 Station Management Data Clock:
The timing reference for MDIO. All data transfers on MDIO are synchronized to the
rising edge of this clock.
PHYINTN I2 46 Interrupt signal from PHY, active low.
TXCLK I2 69 A clock from Giga-PHY operates in MII mode.
If Giga-PHY provides clock for 10/100M in MII mode, AX88180 can use this pin as
reference clock. For normal operation, to connect TXCLK of Giga-PHY with this
pin.
2.3 Host Interface
Table 2 : Host Interface signals group
Pin Name Type Pin NO
Pin Description
INTN TSO, 8mA 102 Interrupt to host system
When the polarity is active high, this signal must be pulled low, otherwise pulled
high in active low environment. Software set the bit6 of command register (CMD) to
response the polarity.
RST_N I3 103 Reset signal: active low.
HCLK I3 104 Reference Clock. This clock may be from host (synchronous mode) or the output of
stand-alone OSC (asynchronous mode).
WAKEUP TSO, 8mA 115 Wake-up signal to system. When the polarity of system is active high, this signal
must be pulled low, otherwise pulled high in active low environment. Software set
the bit0 of command register (CMD) to response the polarity.
HD0 IO3, 8mA 19 Data bus bit0.
HD1 IO3, 8mA 18 Data bus bit1.
HD2 IO3, 8mA 17 Data bus bit2.
HD3 IO3, 8mA 16 Data bus bit3.
HD4 IO3, 8mA 15 Data bus bit4.
HD5 IO3, 8mA 14 Data bus bit5.
HD6 IO3, 8mA 12 Data bus bit6.
HD7 IO3, 8mA 11 Data bus bit7.
HD8 IO3, 8mA 10 Data bus bit8.
HD9 IO3, 8mA 9 Data bus bit9.
HD10 IO3, 8mA 7 Data bus bit10.
HD11 IO3, 8mA 6 Data bus bit11.
HD12 IO3, 8mA 5 Data bus bit12.
HD13 IO3, 8mA 3 Data bus bit13.
HD14 IO3, 8mA 2 Data bus bit14.
HD15 IO3, 8mA 128 Data bus bit15.
HD16 IO3, 8mA 127 Data bus bit16, internal pull down. *
HD17 IO3, 8mA 126 Data bus bit17, internal pull down. *
HD18 IO3, 8mA 125 Data bus bit18, internal pull down. *
HD19 IO3, 8mA 124 Data bus bit19, internal pull down. *
HD20 IO3, 8mA 122 Data bus bit20, internal pull down. *
HD21 IO3, 8mA 121 Data bus bit21, internal pull down. *
HD22 IO3, 8mA 120 Data bus bit22, internal pull down. *
HD23 IO3, 8mA 118 Data bus bit23, internal pull down. *
HD24 IO3, 8mA 116 Data bus bit24, internal pull down. *
HD25 IO3, 8mA 114 Data bus bit25, internal pull down. *
剩余46页未读，继续阅读
ququ1
- 粉丝: 1
- 资源: 1
我的内容管理
展开
最新资源
- C++多态实现机制详解：虚函数与早期绑定
- Java多线程与异常处理详解
- 校园导游系统：无向图实现最短路径探索
- SQL2005彻底删除指南：避免重装失败
- GTD时间管理法：提升效率与组织生活的关键
- Python进制转换全攻略：从10进制到16进制
- 商丘物流业区位优势探究：发展战略与机遇
- C语言实训：简单计算器程序设计
- Oracle SQL命令大全：用户管理、权限操作与查询
- Struts2配置详解与示例
- C#编程规范与最佳实践
- C语言面试常见问题解析
- 超声波测距技术详解：电路与程序设计
- 反激开关电源设计：UC3844与TL431优化稳压
- Cisco路由器配置全攻略
- SQLServer 2005 CTE递归教程：创建员工层级结构
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
