5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3 16x2
Bottom side Cap
SCKP SCKNSVREF
SVREF
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SBA0
SBA1
SBA2
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SBA0
SBA1
SBA2
SWE
SCAS
SRAS
SCS0
SCKE0
SVREF
SVREF
SODT0
SWE
SCAS
SRAS
SCS0
SCKE0
SVREF
SVREF
SODT0
SCKP
SCKN
SCKP
SCKN
SDQS0P
SDQS0N
SDQS1P
SDQS1N
SDQM0
SDQM1
SODT1
SCS1
SCKE1
SRST
SODT1
SCKE1
SCS1
SRST
SDQS3P
SDQS3N
SDQS2P
SDQS2N
SDQM2
SDQM3
SA10
SA11
SA12
SA13
SA14
SA15
SDQ10
SDQ9
SDQ8
SDQ12
SDQ11
SDQ15
SDQ14
SDQ13
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA9
SA8
SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SBA0
SBA1
SBA2
SCAS
SRAS
SRST
SODT1
SWE
SVREF
SCS1
SCS0
SCKP
SCKN
SCKE0
SCKE1
SODT0
SDQS3P
SDQS3N
SDQS2P
SDQS2N
SDQS0P
SDQS0N
SDQS1P
SDQS1N
SDQM2
SDQM3
SDQM0
SDQM1
SVREF
SDQ7
SDQ2
SDQ6
SDQ4
SDQ14
SDQ9
SDQ3
SDQ1
SDQ0
SDQ5
SDQ10
SDQ15
SDQ8
SDQ13
SDQ11
SDQ12
SDQ17
SDQ23
SDQ19
SDQ20
SDQ28
SDQ24
SDQ18
SDQ21
SDQ16
SDQ22
SDQ26
SDQ31
SDQ27
SDQ29
SDQ25
SDQ30
VCC-DRAM
GND
VCC-DRAM
GND
GND
GND
VCC-DRAM
GND
VCC-DRAM
GND
GND
VCC-DRAM
GND
GND
VCC-DRAM
GNDGND
GND
VCC-DRAM
GND
VCC-DRAM
GND
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
DDR3 16X2
A64-STD
A3
4 18Wednesday, July 15, 2015
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
DDR3 16X2
A64-STD
A3
4 18Wednesday, July 15, 2015
Design Name
Size Page Name Rev
Date: Sheet of
AllWinner Technology Co.,Ltd
DDR3 16X2
A64-STD
A3
4 18Wednesday, July 15, 2015
DC14
10uF
C0603
DC3
1uF
C0402
DC4
1uF
C0402
DU1
DDR3-FBGA96
BGA96P0_80B11_00X14_00
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10
L7
A11
R7
A12
N7
A13
T3
A14
T7
A15
M7
BA0
M2
BA1
N8
BA2
M3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
CK
J7
CK#
K7
WE
L3
RAS#
J3
CAS#
K3
CS#
L2
CKE
K9
VREFCA
M8
VREFDQ
H1
ODT
K1
VDDQ#1
A1
VDDQ#2
C1
VDDQ#3
F1
VDDQ#4
D2
VDDQ#5
H2
VDDQ#6
A8
VDDQ#7
H9
VDDQ#8
E9
VDDQ#9
C9
VDD#2
R1
VDD#1
N1
VDD#3
B2
VDD#4
K2
VDD#5
G7
VDD#6
K8
VDD#7
D9
VDD#8
N9
VDD#9
R9
VSSQ#1
B1
VSSQ#2
D1
VSSQ#3
G1
VSSQ#4
E2
VSSQ#5
D8
VSSQ#6
E8
VSSQ#7
B9
VSSQ#8
F9
VSSQ#9
G9
VSS#1
E1
VSS#2
M1
VSS#3
P1
VSS#4
T1
VSS#5
J2
VSS#6
B3
VSS#7
G8
VSS#8
J8
VSS#9
A9
VSS#10
M9
VSS#11
P9
VSS#12
T9
DQSL
F3
DQSL#
G3
DQSU
C7
DQSU#
B7
DML
E7
DMU
D3
ODT1
J1
CS1#
L1
CKE1
J9
ZQ1
L9
ZQ
L8
RESET
T2
DR8 100R R0402
DR3
240-1%
R0402
DC15
1uF
C0402
DC12
104
C0402
DC19
104
C0402
DC20
104
C0402
DR1
240-1%
R0402
DC11
104
C0402
DC13
104
C0402
DC26
104
C0402
DC23
104
C0402
DC10
1uF
C0402
DR7
2K-1%
R0402
DC5
104
C0402
DC1
104
C0402
DC24
104
C0402
DC9
1uF
C0402
DC8
10uF
C0603
DC21
1uF
C0402
DR2
240-1%
R0402
DC22
1uF
C0402
A64
U1A
SA4
P6
SA5
G4
SA6
F3
SA7
E4
SDQ0
L3
SDQ1
G1
SDQ10
T1
SDQ11
R2
SDQ12
N3
SDQ13
N2
SA2
N5
SA3
N6
SDQ14
N1
SDQ15
M2
SDQ16
E3
SDQ17
F2
SDQ18
E2
SDQ19
E1
SDQ2
H3
SDQ20
B1
SDQ21
B2
SDQ22
A2
SDQ23
B3
SWE
C8
SVREF
G5
SDQ3
K1
SDQ4
H2
SDQ5
H1
SDQ6
L1
SRST
D10
SDQS0N
K2
SDQS1P
P1
SDQS1N
P2
SDQS2P
D2
SDQS2N
D1
SDQS3P
B6
SZQ
U1
SDQS3N
B5
SODT0
D5
SODT1
E7
SRAS
F7
VCC-DRAM0
K6
VCC-DRAM1
L6
VCC-DRAM2
G7
VCC-DRAM3
K7
VCC-DRAM4
L7
VCC-DRAM5
N7
VCC-DRAM6
G8
VCC-DRAM7
J8
VCC-DRAM8
L8
SA0
P5
SA1
R4
SDQ7
L2
SDQ8
T3
SDQ9
T2
SDQM0
J2
SDQM1
P3
SDQM2
C2
SDQM3
B7
SDQS0P
K3
SA10
M4
SA11
U4
SA12
K5
SA13
E8
SA14
K4
SA15
T4
SA8
D3
SA9
C4
SBA0
D8
SBA1
R3
SBA2
C6
SCAS
C9
SCKP
G2
SCKN
G3
SCKE0
J3
SCKE1
H6
SCS0
E5
SCS1
H5
SDQ27
A5
SDQ26
A4
SDQ25
B4
SDQ24
C5
SDQ28
A7
SDQ29
A8
SDQ30
B8
SDQ31
B9
VCC-DRAM9
N8
VCC-DRAM10
G9
DC6
104
C0402
DC17
104
C0402
DR6
2K-1%
R0402
DR5
240-1%
R0402
DC16
1uF
C0402
DC18
104
C0402
DR4
240-1%
R0402
DU2
DDR3-FBGA96
BGA96P0_80B11_00X14_00
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10
L7
A11
R7
A12
N7
A13
T3
A14
T7
A15
M7
BA0
M2
BA1
N8
BA2
M3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
CK
J7
CK#
K7
WE
L3
RAS#
J3
CAS#
K3
CS#
L2
CKE
K9
VREFCA
M8
VREFDQ
H1
ODT
K1
VDDQ#1
A1
VDDQ#2
C1
VDDQ#3
F1
VDDQ#4
D2
VDDQ#5
H2
VDDQ#6
A8
VDDQ#7
H9
VDDQ#8
E9
VDDQ#9
C9
VDD#2
R1
VDD#1
N1
VDD#3
B2
VDD#4
K2
VDD#5
G7
VDD#6
K8
VDD#7
D9
VDD#8
N9
VDD#9
R9
VSSQ#1
B1
VSSQ#2
D1
VSSQ#3
G1
VSSQ#4
E2
VSSQ#5
D8
VSSQ#6
E8
VSSQ#7
B9
VSSQ#8
F9
VSSQ#9
G9
VSS#1
E1
VSS#2
M1
VSS#3
P1
VSS#4
T1
VSS#5
J2
VSS#6
B3
VSS#7
G8
VSS#8
J8
VSS#9
A9
VSS#10
M9
VSS#11
P9
VSS#12
T9
DQSL
F3
DQSL#
G3
DQSU
C7
DQSU#
B7
DML
E7
DMU
D3
ODT1
J1
CS1#
L1
CKE1
J9
ZQ1
L9
ZQ
L8
RESET
T2
DC2
10uF
C0603
DC7
104
C0402
DC25
104
C0402
请尽量使用Allwinner提供的DDR Layout参考
模板;否则请严格遵守DDR Layout Guide。
采用Allwinner DDR Layout模板,红色框中的元器件位号不能变。