PCI Express v2.0规范详解：修订历史与发展更新

PCI.Express.v2.0规范

需积分: 47 93 浏览量更新于2024-07-29 收藏 3.54MB PDF 举报

PCIExpress (PCIe) v2.0规范是一个在2006年9月11日发布的标准，它代表着高性能计算机总线接口的显著升级，从PCI Express 1.x版本的基础上发展而来。这一版本的主要修订历史包括以下几个关键特性： 1. **Trusted Configuration Space**（受信任配置空间）：这是在2005年3月23日引入的一个概念，旨在增强系统的安全性，允许设备管理器对设备的配置数据进行更严格的控制和验证，更新日期至2005年7月1日。 2. **Link Speed Management**：此功能允许系统动态调整PCIe链路的速度，以适应不同的工作负载需求，提高带宽利用率，更新日期是2005年8月25日。 3. **PCIe Capability Structure Expansion**：这一扩展增强了设备的能力描述符结构，以便更好地支持新功能和技术，分别在2005年3月21日和8月19日进行了更新。 4. **Link Bandwidth Notification Mechanism**：这是一种机制，用于通知设备链路带宽的变化，以便应用程序能够及时调整其性能，首次提出于2005年4月20日，后续更新至8月26日。 5. **Errata for PCIExpress Base Specification, Revision 1.1**：随着v2.0规范的发布，也对先前版本的错误进行了修正，这表明规范的不断完善和优化过程。在2005年9月16日的0.7版本中，加入了更多功能和修正，如PCIe Capability Structure Expansion的进一步完善、Link Bandwidth Notification Mechanism的更新、Completion Timeout Control Capability的新增以及Function Level Reset (FLR) 的功能，以及PCIExpress Access Control Services (ACS) 的引入。这些更改旨在提升系统的稳定性和性能。到了0.7a版本，主要是对0.7草案中的剪切和粘贴错误进行了纠正，显示了规范制定者对于细节的严谨态度和对质量的持续关注。 PCIExpress v2.0规范的发布不仅提升了数据传输速度，还引入了一系列增强功能，包括安全性和管理能力的改进，反映了PCIe技术的快速发展和对现代计算环境的适应性。这个标准对于PC硬件制造商和系统集成商来说至关重要，因为它定义了设备如何高效地连接到主板，共享系统资源，并与主机通信。

PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9

FIGURE 7-99: TRUSTED CONFIGURATION SPACE HEADER .......................................................... 586

FIGURE 7-100: CONFIGURATION ACCESS CORRELATION TRUSTED CAPABILITY ........................ 587

FIGURE 7-101: CONFIGURATION ACCESS CORRELATION TRUSTED CAPABILITY HEADER........... 588

IGURE 7-102: DEVICE CORRELATION REGISTER ........................................................................ 589

IGURE 7-103: PCI EXPRESS VSTC STRUCTURE........................................................................ 590

FIGURE 7-104: VENDOR-SPECIFIC TRUSTED CAPABILITY HEADER............................................. 590

FIGURE 7-105: VENDOR-SPECIFIC HEADER ................................................................................ 591

FIGURE 7-106: VSTC VENDOR ID.............................................................................................. 593

IGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER

COMMUNICATION MODELS.................................................................................................. 596

FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND

CONGESTION........................................................................................................................ 597

FIGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS

............................................................................................................................................. 602

IGURE C-1: SCRAMBLING SPECTRUM FOR DATA VALUE OF 0................................................... 621

FIGURE E-1: GATING TCS ACCESS VIA TPM............................................................................. 628

PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9

Tables

TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 48

ABLE 2-2: FMT[1:0] FIELD VALUES ............................................................................................ 53

TABLE 2-3: FMT[1:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 53

ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 54

ABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 58

TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 58

TABLE 2-7: HEADER FIELD LOCATIONS FOR ID ROUTING............................................................. 59

TABLE 2-8: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 61

ABLE 2-9: ORDERING ATTRIBUTES ............................................................................................. 66

ABLE 2-10: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 66

TABLE 2-11: DEFINITION OF TC FIELD ENCODINGS...................................................................... 67

TABLE 2-12: MESSAGE ROUTING.................................................................................................. 71

TABLE 2-13: INTX MECHANISM MESSAGES ................................................................................. 73

TABLE 2-14: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 75

TABLE 2-15: POWER MANAGEMENT MESSAGES........................................................................... 76

TABLE 2-16: ERROR SIGNALING MESSAGES ................................................................................. 77

TABLE 2-17 UNLOCK MESSAGE.................................................................................................... 78

TABLE 2-18: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 78

TABLE 2-19: VENDOR_DEFINED MESSAGES................................................................................. 80

TABLE 2-20: IGNORED MESSAGES ................................................................................................ 81

TABLE 2-21: COMPLETION STATUS FIELD VALUES....................................................................... 83

TABLE 2-22: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES............................ 97

TABLE 2-23: CALCULATING LOWER ADDRESS FROM 1

DW BE................................................. 98

TABLE 2-24: ORDERING RULES SUMMARY TABLE...................................................................... 103

TABLE 2-25: TC TO VC MAPPING EXAMPLE .............................................................................. 111

TABLE 2-26: FLOW CONTROL CREDIT TYPES ............................................................................. 114

TABLE 2-27: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 115

TABLE 2-28: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 116

ABLE 2-29: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 123

ABLE 2-30: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 123

TABLE 2-31: MAPPING OF BITS INTO ECRC FIELD ..................................................................... 126

TABLE 3-1: DLLP TYPE ENCODINGS.......................................................................................... 145

ABLE 3-2: MAPPING OF BITS INTO CRC FIELD.......................................................................... 148

TABLE 3-3: MAPPING OF BITS INTO LCRC FIELD ....................................................................... 152

TABLE 3-4: UNADJUSTED REPLAY_TIMER LIMITS FOR 2.5 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 157

TABLE 3-5: UNADJUSTED REPLAY_TIMER LIMITS FOR 5.0 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 157

TABLE 3-6: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 2.5 GT/S MODE

OPERATIONS BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................. 167

PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9

TABLE 3-7: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 5.0 GT/S MODE

OPERATIONS BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................. 168

TABLE 4-1: SPECIAL SYMBOLS ................................................................................................... 174

ABLE 4-2: TS1 ORDERED SET ................................................................................................... 181

ABLE 4-3: TS2 ORDERED SET ................................................................................................... 183

TABLE 4-4: ELECTRICAL IDLE ORDERED SET (EIOS) FOR 2.5 GT/S DATA RATE....................... 185

TABLE 4-5: ELECTRICAL IDLE ORDERED SET (EIOS) FOR DATA RATES GREATER THAN 2.5 GT/S

............................................................................................................................................. 186

ABLE 4-6: ELECTRICAL IDLE EXIT SEQUENCE (EIEOS) ORDERED SET (ONLY FOR DATA RATES

OTHER THAN 2.5 GT/S) ....................................................................................................... 186

TABLE 4-7: ELECTRICAL IDLE INFERENCE CONDITIONS.............................................................. 187

TABLE 4-8: LINK STATUS MAPPED TO THE LTSSM................................................................... 196

TABLE 4-9: PCI EXPRESS 2.5 GT/S / 5.0 GT/S INTEROPERABILITY MATRIX ............................... 246

ABLE 4-10: 2.5 AND 5.0 GT/S TRANSMITTER SPECIFICATIONS ................................................. 252

ABLE 4-11: 5.0 GT/S LIMITS FOR COMMON REFCLK RX ARCHITECTURE.................................. 267

TABLE 4-12: 5.0 GT/S TOLERANCING LIMITS FOR DATA CLOCKED RX ARCHITECTURE............ 268

TABLE 4-13: 2.5 AND 5.0 GT/S PCI EXPRESS RECEIVER SPECIFICATIONS .................................. 270

TABLE 4-14: WORST CASE TX CORNERS FOR CHANNEL SIMULATION........................................ 285

TABLE 4-15: REFCLK FILTERING FUNCTIONS............................................................................. 290

TABLE 4-16: DIFFERENCE FUNCTION PARAMETERS APPLIED TO REFCLK MEASUREMENT ......... 292

TABLE 4-17: REFCLK PARAMETERS FOR COMMON CLOCK ARCHITECTURE AT 5.0 GT/S............ 292

TABLE 4-18: PLL PARAMETERS FOR DATA CLOCKED ARCHITECTURE....................................... 294

TABLE 4-19: REFCLK PARAMETERS FOR DATA CLOCKED ARCHITECTURE ................................. 294

TABLE 5-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES........................... 302

TABLE 5-2: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK AND COMPONENTS .. 308

TABLE 5-3: ENCODING OF THE ASPM SUPPORT FIELD ............................................................... 333

TABLE 5-4: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION FIELD ..................................... 334

TABLE 5-5: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION FIELD .............................. 334

TABLE 5-6: ENCODING OF THE L0S EXIT LATENCY FIELD .......................................................... 335

TABLE 5-7: ENCODING OF THE L1 EXIT LATENCY FIELD ............................................................ 335

ABLE 5-8: ENCODING OF THE ENDPOINT L0S ACCEPTABLE LATENCY FIELD............................ 335

TABLE 5-9: ENCODING OF THE ENDPOINT L1 ACCEPTABLE LATENCY FIELD.............................. 336

ABLE 5-10: ENCODING OF THE ASPM CONTROL FIELD............................................................ 336

ABLE 5-11: POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS ....................................... 339

TABLE 6-1: ERROR MESSAGES.................................................................................................... 349

TABLE 6-2: PHYSICAL LAYER ERROR LIST ................................................................................. 361

ABLE 6-3: DATA LINK LAYER ERROR LIST............................................................................... 361

TABLE 6-4: TRANSACTION LAYER ERROR LIST .......................................................................... 362

ABLE 6-5: ELEMENTS OF HOT-PLUG ......................................................................................... 391

TABLE 6-6: ATTENTION INDICATOR STATES ............................................................................... 392

TABLE 6-7: POWER INDICATOR STATES ...................................................................................... 393

ABLE 6-8: ACS P2P REQUEST REDIRECT AND ACS P2P EGRESS CONTROL INTERACTIONS..... 418

TABLE 7-1: ENHANCED CONFIGURATION ADDRESS MAPPING .................................................... 427

ABLE 7-2: REGISTER AND REGISTER BIT-FIELD TYPES............................................................. 437

ABLE 7-3: COMMAND REGISTER ............................................................................................... 440

ABLE 7-4: STATUS REGISTER .................................................................................................... 442

PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9

TABLE 7-5: SECONDARY STATUS REGISTER ............................................................................... 448

TABLE 7-6: BRIDGE CONTROL REGISTER.................................................................................... 450

TABLE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS ............... 451

ABLE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS ........ 452

ABLE 7-9: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................... 455

TABLE 7-10: PCI EXPRESS CAPABILITIES REGISTER................................................................... 456

TABLE 7-11: DEVICE CAPABILITIES REGISTER............................................................................ 460

TABLE 7-12: DEVICE CONTROL REGISTER.................................................................................. 464

ABLE 7-13: DEVICE STATUS REGISTER ..................................................................................... 471

ABLE 7-14: LINK CAPABILITIES REGISTER................................................................................ 473

TABLE 7-15: LINK CONTROL REGISTER ...................................................................................... 478

TABLE 7-16: LINK STATUS REGISTER ......................................................................................... 484

TABLE 7-17: SLOT CAPABILITIES REGISTER ............................................................................... 487

ABLE 7-18: SLOT CONTROL REGISTER...................................................................................... 490

ABLE 7-19: SLOT STATUS REGISTER......................................................................................... 493

TABLE 7-20: ROOT CONTROL REGISTER..................................................................................... 495

TABLE 7-21: ROOT CAPABILITIES REGISTER............................................................................... 497

TABLE 7-22: ROOT STATUS REGISTER........................................................................................ 497

TABLE 7-23: DEVICE CAPABILITIES 2 REGISTER......................................................................... 498

TABLE 7-24: DEVICE CONTROL 2 REGISTER................................................................................ 500

TABLE 7-25: LINK CONTROL 2 REGISTER ................................................................................... 502

TABLE 7-26: LINK STATUS 2 REGISTER ...................................................................................... 504

TABLE 7-27: PCI EXPRESS ENHANCED CAPABILITY HEADER..................................................... 506

TABLE 7-28: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER......................... 509

TABLE 7-29: UNCORRECTABLE ERROR STATUS REGISTER ......................................................... 510

TABLE 7-30: UNCORRECTABLE ERROR MASK REGISTER............................................................ 511

TABLE 7-31: UNCORRECTABLE ERROR SEVERITY REGISTER ...................................................... 513

TABLE 7-32: CORRECTABLE ERROR STATUS REGISTER.............................................................. 514

TABLE 7-33: CORRECTABLE ERROR MASK REGISTER................................................................. 515

TABLE 7-34: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER.................................. 516

ABLE 7-35: HEADER LOG REGISTER ......................................................................................... 517

TABLE 7-36: ROOT ERROR COMMAND REGISTER ....................................................................... 518

ABLE 7-37: ROOT ERROR STATUS REGISTER ............................................................................ 520

ABLE 7-38: ERROR SOURCE IDENTIFICATION REGISTER ........................................................... 522

TABLE 7-39: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER........................................... 525

TABLE 7-40: PORT VC CAPABILITY REGISTER 1......................................................................... 526

ABLE 7-41: PORT VC CAPABILITY REGISTER 2......................................................................... 527

TABLE 7-42: PORT VC CONTROL REGISTER ............................................................................... 528

ABLE 7-43: PORT VC STATUS REGISTER .................................................................................. 529

TABLE 7-44: VC RESOURCE CAPABILITY REGISTER................................................................... 530

TABLE 7-45: VC RESOURCE CONTROL REGISTER....................................................................... 531

ABLE 7-46: VC RESOURCE STATUS REGISTER.......................................................................... 534

TABLE 7-47: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE ..................... 535

ABLE 7-48: LENGTH OF THE VC ARBITRATION TABLE ............................................................. 535

ABLE 7-49: LENGTH OF PORT ARBITRATION TABLE ................................................................. 537

ABLE 7-50: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER .................................. 538

PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9

TABLE 7-51: SERIAL NUMBER REGISTER.................................................................................... 539

TABLE 7-52: ROOT COMPLEX LINK DECLARATION ENHANCED CAPABILITY HEADER ............... 542

TABLE 7-53: ELEMENT SELF DESCRIPTION REGISTER ................................................................. 543

ABLE 7-54: LINK DESCRIPTION REGISTER ................................................................................ 545

ABLE 7-55: LINK ADDRESS FOR LINK TYPE 1 ........................................................................... 547

TABLE 7-56: ROOT COMPLEX INTERNAL LINK CONTROL ENHANCED CAPABILITY HEADER ...... 549

TABLE 7-57: ROOT COMPLEX LINK CAPABILITIES REGISTER ..................................................... 550

TABLE 7-58: ROOT COMPLEX LINK CONTROL REGISTER............................................................ 552

ABLE 7-59: ROOT COMPLEX LINK STATUS REGISTER............................................................... 553

ABLE 7-60: POWER BUDGETING ENHANCED CAPABILITY HEADER .......................................... 555

TABLE 7-61: POWER BUDGETING DATA REGISTER..................................................................... 556

TABLE 7-62: POWER BUDGET CAPABILITY REGISTER................................................................. 558

TABLE 7-63: ACS EXTENDED CAPABILITY HEADER................................................................... 559

ABLE 7-64: ACS CAPABILITY REGISTER................................................................................... 560

ABLE 7-65: ACS CONTROL REGISTER ...................................................................................... 561

TABLE 7-66: EGRESS CONTROL VECTOR .................................................................................... 563

TABLE 7-67: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION ENHANCED

CAPABILITY HEADER........................................................................................................... 565

TABLE 7-68: MFVC ENHANCED CAPABILITY HEADER............................................................... 567

TABLE 7-69: PORT VC CAPABILITY REGISTER 1......................................................................... 568

TABLE 7-70: PORT VC CAPABILITY REGISTER 2......................................................................... 569

TABLE 7-71: PORT VC CONTROL REGISTER ............................................................................... 570

TABLE 7-72: PORT VC STATUS REGISTER .................................................................................. 571

TABLE 7-73: VC RESOURCE CAPABILITY REGISTER................................................................... 572

TABLE 7-74: VC RESOURCE CONTROL REGISTER....................................................................... 574

TABLE 7-75: VC RESOURCE STATUS REGISTER.......................................................................... 576

TABLE 7-76: LENGTH OF FUNCTION ARBITRATION TABLE ......................................................... 577

TABLE 7-77: VENDOR-SPECIFIC ENHANCED CAPABILITY HEADER............................................. 579

TABLE 7-78: VENDOR-SPECIFIC HEADER.................................................................................... 580

TABLE 7-79: RCRB HEADER ENHANCED CAPABILITY HEADER................................................. 582

ABLE 7-80: VENDOR ID AND DEVICE ID................................................................................... 582

TABLE 7-81: RCRB CAPABILITIES.............................................................................................. 583

ABLE 7-82: RCRB CONTROL .................................................................................................... 583

ABLE 7-83: TRUSTED CONFIGURATION SPACE CAPABILITY HEADER ....................................... 585

TABLE 7-84: DEVICE CORRELATION REGISTER........................................................................... 585

TABLE 7-85: TRUSTED CONFIGURATION REGISTERS................................................................... 586

ABLE 7-86: CONFIGURATION ACCESS CORRELATION TRUSTED CAPABILITY HEADER ............. 588

TABLE 7-87: DEVICE CORRELATION REGISTER........................................................................... 589

ABLE 7-88: VENDOR-SPECIFIC TRUSTED CAPABILITY HEADER................................................ 590

TABLE 7-89: VENDOR-SPECIFIC HEADER.................................................................................... 592

TABLE 7-90: VSTC VENDOR ID ................................................................................................. 593

ABLE A-1: ISOCHRONOUS BANDWIDTH RANGES AND GRANULARITIES.................................... 599

TABLE B-1: 8B/10B DATA SYMBOL CODES................................................................................. 607

ABLE B-2: 8B/10B SPECIAL CHARACTER SYMBOL CODES ........................................................ 615

剩余631页未读，继续阅读

zfl864407

粉丝: 0
资源: 1

PCI Express v2.0规范详解：修订历史与发展更新

PCI Express Base Specification Revision 2.0 协议规范

PCI.Express.Base.Specification.v2.0.pdf

pci-express base spec v2.0

PCI.Express.Base.Specification.v3.0-draft.rar_pci_pci express ba

PCI Express 2.0 Base Specification v2.0修订历史与关键更新

PCI EXPRESS 2.0 规范

深入了解PCI Express M.2技术规范v1.1

PCI Express 2.0基础规范修订版

PCI Express 2.0规范修订历史与关键特性

深入探究PCI Express 2.0与5.0规范文件下载

最新资源