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首页CC1101:超低功耗300-900MHz RF TX/RX解决方案
CC1101:超低功耗300-900MHz RF TX/RX解决方案
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更新于2024-08-02
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CC1101 RF TX/RX是一款专为极低功耗无线应用设计的低频射频收发器,特别适用于315/433/868/915 MHz ISM(工业、科学和医疗)和SRD(短程设备)频段,它在智能家居自动化、无线报警和安全系统、工业监控与控制、自动计量读取(AMR)以及无线M-Bus等多个领域具有广泛的应用。这款芯片以其出色的性能提升而脱颖而出,相较于CC1100有显著改进。 主要特点包括: 1. 改进的杂散响应:CC1101通过优化设计,减少了非预期频率的信号干扰,提高了信号传输的纯净度,这对于需要高度可靠性的通信系统至关重要。 2. 卓越的相位噪声和邻道功率性能:更优秀的相位噪声控制使得信号在传输过程中受到的噪声影响减小,从而提升了邻道功率(Adjacent Channel Power, ACP),确保了在多个频道之间的干扰抑制。 3. 增强的输入饱和水平:更高的输入饱和能力意味着CC1101能处理更大的信号强度,提高了接收灵敏度,使设备在信号较弱的环境下仍能稳定工作。 4. 改良的输出功率控制:输出功率的平滑调整特性使得CC1101能根据应用需求灵活调整发射功率,既节省能源又确保信号传输距离。 5. 扩展的工作频率范围:相比于CC1100,CC1101支持更宽的频率范围,即400-464 MHz,这为用户提供了更大的灵活性,可以根据不同地区或法规要求选择合适的频段。 CC1101 RF TX/RX是一款高度集成且节能的解决方案,适用于对功耗、信号质量和可编程性有严格要求的无线通信项目。其在低功耗、抗干扰和多频段应用中的优越性能,使其成为物联网(IoT)设备和智能家居等领域的理想选择。
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CC1101
SWRS061E Page 16 of 97
Parameter Min Typ Max Unit Condition/Note
Spurious emissions
conducted, harmonics
not included
315 MHz
433 MHz
868 MHz
915 MHz
< -58
< -53
< -50
< -54
< -56
< -50
< -52
< -53
< -51
< -54
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Measured with +10 dBm CW at 315 MHz and 433 MHz
Frequencies below 960 MHz
Frequencies above 960 MHz
Frequencies below 1 GHz
Frequencies above 1 GHz
Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
Measured with +12 dBm CW at 868 MHz
Frequencies below 1 GHz
Frequencies above 1 GHz
Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
All radiated spurious emissions are within the limits of ETSI.
The peak conducted spurious emission is -53 dBm at 699
MHz, which is in a frequency band limited to -54 dBm by EN
300 220. An alternative filter can be used to reduce the
emission at 699 MHz below -54 dBm, for conducted
measurements, and is shown in Figure 1. See more
information in DN017 [12]
Measured with +11 dBm CW at 915 MHz
Frequencies below 960 MHz
Frequencies above 960 MHz
TX latency 8 bit Serial operation. Time from sampling the data on the
transmitter data input pin until it is observed on the RF output
ports
Table 10: RF Transmit Section
Table 11: Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
Table 12: Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
Supply Voltage
VDD = 1.8 V
Supply Voltage
VDD = 3.0 V
Supply Voltage
VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Output Power [dBm],
PATABLE=0xC0, +12 dBm
12 11 10 12 12 11 12 12 11
Output Power [dBm],
PATABLE=0xC5, +10 dBm
11 10 9 11 10 10 11 10 10
Output Power [dBm],
PATABLE=0x50, 0 dBm
1 0 -1 2 1 0 2 1 0
Supply Voltage
VDD = 1.8 V
Supply Voltage
VDD = 3.0 V
Supply Voltage
VDD = 3.6 V
Temperature [°C] -40 25 85 -40 25 85 -40 25 85
Output Power [dBm],
PATABLE=0xC0, +11 dBm
11 10 10 12 11 11 12 11 11
Output Power [dBm],
PATABLE=0x8E, +0 dBm
2 1 0 2 1 0 2 1 0
![](https://csdnimg.cn/release/download_crawler_static/2058291/bg11.jpg)
CC1101
SWRS061E Page 17 of 97
4.4 Crystal Oscillator
T
A
= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ( [2]
and [3]).
Table 13: Crystal Oscillator Parameters
4.5 Low Power RC Oscillator
T
A
= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ( [2]
and [3]).
Table 14: RC Oscillator Parameters
Parameter Min Typ Max Unit Condition/Note
Crystal frequency 26 26 27 MHz
Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal
loading, c) aging, and d) temperature dependence. The
acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100
Ω
Start-up time 150 µs This parameter is to a large degree crystal dependent. Measured
on the CC1101EM reference designs ( [2] and [3]) using crystal
AT-41CD2 from NDK
Parameter Min Typ Max Unit Condition/Note
Calibrated frequency 34.7 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL
frequency divided by 750
Frequency accuracy after
calibration
±1 %
Temperature coefficient +0.5
% / °C
Frequency drift when temperature changes after
calibration
Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after
calibration
Initial calibration time 2 ms
When the RC Oscillator is enabled, calibration is
continuously done in the background as long as
the crystal oscillator is running
![](https://csdnimg.cn/release/download_crawler_static/2058291/bg12.jpg)
CC1101
SWRS061E Page 18 of 97
4.6 Frequency Synthesizer Characteristics
T
A
= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference designs
( [2] and [3]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.
Table 15: Frequency Synthesizer Parameters
4.7 Analog Temperature Sensor
T
A
= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ( [2]
and [3]). Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
Table 16: Analog Temperature Sensor Parameters
Parameter Min Typ Max Unit Condition/Note
Programmed frequency
resolution
397 F
XOSC
/
2
16
412 Hz 26-27 MHz crystal. The resolution (in Hz) is equal
for all frequency bands
Synthesizer frequency
tolerance
±40 ppm Given by crystal used. Required accuracy
(including temperature and aging) depends on
frequency band and channel bandwidth / spacing
RF carrier phase noise –92 dBc/Hz @ 50 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz @ 100 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz @ 200 kHz offset from carrier
RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier
RF carrier phase noise –107 dBc/Hz @ 1 MHz offset from carrier
RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier
RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier
RF carrier phase noise –129 dBc/Hz @ 10 MHz offset from carrier
PLL turn-on / hop time 85.1 88.4 88.4
µs
Time from leaving the IDLE state until arriving in
the RX, FSTXON or TX state, when not
performing calibration. Crystal oscillator running
PLL RX/TX settling time 9.3 9.6 9.6
µs
Settling time for the 1·IF frequency step from RX
to TX
PLL TX/RX settling time 20.7 21.5 21.5
µs
Settling time for the 1·IF frequency step from TX
to RX
PLL calibration time 694 721 721
µs
Calibration can be initiated manually or
automatically before entering or after leaving
RX/TX
Parameter Min Typ Max Unit Condition/Note
Output voltage at –40°C
0.651 V
Output voltage at 0°C
0.747 V
Output voltage at +40°C
0.847 V
Output voltage at +80°C
0.945 V
Temperature coefficient 2.47
mV/°C Fitted from –20 °C to +80 °C
Error in calculated
temperature, calibrated
-2
*
0 2
*
°C From –20 °C to +80 °C when using 2.47 mV / °C, after
1-point calibration at room temperature
*
The indicated minimum and maximum error with 1-
point calibration is based on simulated values for
typical process parameters
Current consumption
increase when enabled
0.3 mA
![](https://csdnimg.cn/release/download_crawler_static/2058291/bg13.jpg)
CC1101
SWRS061E Page 19 of 97
4.8 DC Characteristics
T
A
= 25°C if nothing else stated.
Table 17: DC Characteristics
4.9 Power-On Reset
For proper Power-On-Reset functionality the power supply should comply with the requirements in
Table 18 below. Otherwise, the chip should be assumed to have unknown state until transmitting an
SRES strobe over the SPI interface. See Section on page 49 for further details.
Table 18: Power-On Reset Requirements
Digital Inputs/Outputs Min Max Unit Condition
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD-0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –50 nA Input equals 0V
Logic "1" input current N/A 50 nA Input equals VDD
Parameter Min Typ Max Unit Condition/Note
Power-up ramp-up time 5 ms From 0V until reaching 1.8V
Power off time 1 ms Minimum time between power-on and power-off
![](https://csdnimg.cn/release/download_crawler_static/2058291/bg14.jpg)
CC1101
SWRS061E Page 20 of 97
5 Pin Configuration
The
CC1101
pin-out is shown in Figure 6 and Table 19. See Section 26 for details on the I/O
configuration.
1
20 19 18 17 16
15
14
13
12
11
109876
5
4
3
2
GND
Exposed die
attach pad
SCLK
SO (GDO1)
GDO2
DVDD
DCOUPL
GDO0 (ATEST)
XOSC_Q1
AVDD
XOSC_Q2
AVDD
RF_P
RF_N
GND
AVDD
RBIAS
DGUARD
GND
SI
CSn
AVDD
Figure 6: Pinout Top View
.
Pin # Pin Name Pin type Description
1 SCLK Digital Input Serial configuration interface, clock input
2 SO (GDO1) Digital Output Serial configuration interface, data output
Optional general output pin when CSn is high
3 GDO2
Digital Output Digital output pin for general use:
• Test signals
• FIFO status signals
• Clear channel indicator
• Clock output, down-divided from XOSC
• Serial output RX data
4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling
NOTE: This pin is intended for use with the
CC1101
only. It can not be used
to provide supply voltage to other devices
Note: The exposed die attach pad must be connected to a solid ground plane as this is the main
ground connection for the chip
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