ESMT
(Preliminary) FM6BD4G2GA
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2014
Revision: 0.2 18/167
System Interface Using CE# Don’t Care
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown below. The internal 2,112 byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications that use slow cycle time on the order of μ-seconds, de-activating CE# during the data-loading and serial access
would provide significant savings in power consumption.
Program / Read Operation with “CE# not-care”
Address Information
Data I/O Address
Data In/Out I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
2,112 Byte I/O 0 ~ I/O 7 A0 ~ A7 A8 ~ A11 A12 ~ A19 A20 ~ A27 A28 ~ A30
