AD7810
–3–
REV. A
Timing Characteristics
1, 2
Parameter V
DD
= 5 V ⴞ 10% V
DD
= 3 V ⴞ 10% Units Conditions/Comments
t
1
2.3 2.3 µs (max) Conversion Time Mode 1 Operation (High Speed Mode)
t
2
20 20 ns (min) CONVST Pulsewidth
t
3
25 25 ns (min) SCLK High Pulsewidth
t
4
25 25 ns (min) SCLK Low Pulsewidth
t
5
3
5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time
t
6
3
10 10 ns (max) SCLK Rising Edge to D
OUT
Data Valid Delay
t
7
3
5 5 ns (max) Data Hold Time after Rising Edge SCLK
t
8
3, 4
20 20 ns (max) Bus Relinquish Time After Falling Edge of SCLK
10 10 ns (min)
t
POWER UP
11µs (max) Power-Up Time After Rising Edge of CONVST
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V ± 10% and
0.4 V or 2 V for V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40ⴗC to +105ⴗC, V
REF
= +V
DD
, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(D
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
(V
IN+
, V
IN–
) . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . +125°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . +50°C/W
Lead Temperature Soldering (10 sec) . . . . . . . . . . +260°C
I
OL
200mA
I
OH
200mA
+1.6V
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity Temperature Branding Package
Model Error (LSB) Range Information Options*
AD7810YN ±1 LSB –40°C to +105°C N-8
AD7810YR ±1 LSB –40°C to +105°C SO-8
AD7810YRM ±1 LSB –40°C to +105°C C1Y RM-8