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22.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[3])......... 2216
22.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102..................... 2217
22.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103.................... 2219
22.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108....................... 2220
22.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A ........................................... 2220
22.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................ 2221
22.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[3).. 2222
22.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-
USBTXCSRH[3]) ............................................................................................... 2225
22.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[3])......... 2227
22.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[3).. 2228
22.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-
USBRXCSRH[3]) ............................................................................................... 2231
22.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[3) .......... 2233
22.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[3]) .... 2234
22.6.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[3])... 2235
22.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[3])..... 2236
22.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]-
USBRXINTERVAL[3]) ......................................................................................... 2237
22.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-
USBRQPKTCOUNT[3) ........................................................................................ 2238
22.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340..... 2239
22.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 .... 2240
22.6.46 USB External Power Control Register (USBEPC), offset 0x400 ...................................... 2241
22.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404 ........ 2243
22.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408 ................. 2244
22.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C . 2245
22.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410 ................. 2246
22.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414.................... 2247
22.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418........... 2248
22.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C.................... 2249
22.6.54 USB DMA Select Register (USBDMASEL), offset 0x450 .............................................. 2250
23 Universal Parallel Port (uPP) ............................................................................................ 2252
23.1 Introduction............................................................................................................... 2253
23.1.1 Features Supported........................................................................................... 2253
23.2 Configuring Device Pins................................................................................................ 2254
23.3 Functional Description .................................................................................................. 2254
23.3.1 Functional Block Diagram.................................................................................... 2254
23.3.2 Data Flow ...................................................................................................... 2254
23.3.3 Clock Generation and Control ............................................................................... 2255
23.4 IO Interface and System Requirements.............................................................................. 2257
23.4.1 Pin Multiplexing................................................................................................ 2257
23.4.2 Internal DMA Controller Description ........................................................................ 2257
23.4.3 Protocol Description .......................................................................................... 2259
23.4.4 Data Format.................................................................................................... 2262
23.4.5 Reset Considerations......................................................................................... 2262
23.4.6 Interrupt Support .............................................................................................. 2263
23.4.7 Emulation Considerations .................................................................................... 2264
23.4.8 Transmit and Receive FIFOs ................................................................................ 2264
23.4.9 Transmit and Receive Data (MSG) RAM .................................................................. 2264
23.4.10 Initialization and Operation ................................................................................. 2265
23.5 Registers ................................................................................................................. 2267
23.5.1 UPP Base Addresses......................................................................................... 2267
23.5.2 UPP_REGS Registers........................................................................................ 2268
16
Contents SPRUHX5C–August 2014–Revised September 2015
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