HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10 7 June 9, 2004
struction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 2 levels and is neither part of the
data nor part of the program space, and is neither read
-
able nor writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro
-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al
-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 2 return ad-
dresses are stored).
Data Memory - RAM
The data memory is designed with 49´8 bits
(HT48R05A-1/HT48C05) or 81´8 bits (HT48R06A-1/
HT48C06). The data memory is divided into two func
-
tional groups: special function registers and general
purpose data memory 32´8 (HT48R05A-1/HT48C05)
or 64´8 (HT48R06A-1/HT48C06). Most are read/write,
but some are read only.
The special function registers include the indirect ad
-
dressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis
-
ter (PCL;06H), memory pointer register (MP;01H), ac
-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H). The remain
-
ing space before the 60H (HT48R05A-1/ HT48C05) or
40H (HT48R06A-1/ HT48C06) is reserved for future ex
-
panded usage and reading these locations will get
²00H². The general purpose data memory, addressed
from 60H to 7FH (HT48R05A-1/ HT48C05) or 40H to
7FH (HT48R06A-1/ HT48C06), is used for data and
control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di
-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re
-
sult 00H. Writing indirectly results in no operation.
G e n e r a l P u r p o s e
D A T A M E M O R Y
( 3 2 B y t e s )
S p e c i a l P u r p o s e
D A T A M E M O R Y
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
7 F H
I n d i r e c t A d d r e s s i n g R e g i s t e r
M P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P C
P C C
: U n u s e d
R e a d a s " 0 0 "
5 F H
6 0 H
2 0 H
H T 4 8 R 0 5 A - 1 / H T 4 8 C 0 5
RAM Mapping for HT48R05A-1/HT48C05
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