1553B芯片手册：Enhanced Mini-ACE系列架构参考

芯片手册

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1553B芯片手册MN-6186X-001是Data Device Corporation（DDC）出品的一款Enhanced Miniature Advanced Communications Engine (Enhanced Mini-ACE® Series)的用户指南，专注于该系列的Volume 1 - Architectural Reference部分。该手册详细介绍了1553B总线控制芯片的设计、功能特性和操作原理，它是专为满足高级通信应用的需求而设计的，尤其是在实时数据传输和系统集成领域。 1553B总线是一种串行通信接口标准，最初由美国军方开发，用于飞机和航天器的系统级数据交换。它以其高可靠性和容错能力而闻名，能够在复杂的工业环境中稳定工作。Enhanced Mini-ACE系列芯片作为新一代产品，可能在原有的1553B基础上增加了增强功能，例如更高的数据速率、更低的功耗和扩展的接口选项，以适应现代电子设备的高速和高效需求。手册中包含了芯片的主要特性，如其物理架构、数据传输协议、错误检测与纠正机制、以及中断管理和地址编码方式等关键知识点。此外，用户指南还强调了设计者在使用该芯片时需要注意的事项，如电源管理、引脚配置和信号处理规则，以及如何确保与其他系统组件的兼容性。值得注意的是，手册中的信息虽然被认为准确，但用户在实际应用中仍需谨慎对待，因为规格可能会根据技术进步随时更新。若需获取最新资料，应访问DDC的官方网站www.ddc-web.com。版权方面，所有内容未经Data Device Corporation书面许可，不得复制或通过任何形式传播，包括电子、机械、影印、录音等。手册提供了多种联系方式以供技术支持，包括美国总部、英国、法国和德国的客户服务电话和传真号码，以便用户在遇到问题时寻求帮助。这份1553B芯片手册MN-6186X-001是硬件工程师、系统集成者和维护人员不可或缺的参考资料，它详尽地阐述了如何有效利用Enhanced Mini-ACE系列芯片实现高效的1553B通信，并强调了合规使用的重要性。

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INTRODUCTION

Data Device Corporation 3 EMA User’s Guide (Volume 1)

Figure 2. Mini-ACE Mark3 and Micro-ACE-TE Series Block Diagram

(Shown with +3.3V Transceivers)

Figure 3. Total-ACE Block Diagram

Data Device Corporation 5 EMA User’s Guide (Volume 1)

3 FUNCTIONAL OVERVIEW

The BU-61743/61745 RT, and BU-61843/61845/61864/61865 BC/RT/MT Enhanced

Mini-ACE (BU-61740B RT, and BU-61840B/61860B BC/RT/MT Micro-ACE), BU-

64743/64745 RT, and BU-64843/64845/64863 BC/RT/MT Mini-ACE Mark3 (BU-

64840B/64843B/64860B/64863B BC/RT/MT Micro-ACE-TE), and the BU-64843T

Total-ACE family of MIL-STD-1553 terminals comprise a complete integrated

interface between a host processor and a MIL-STD-1553 bus.

The BU-61743/61745 RT, and BU-61843/61845/61864/61865 BC/RT/MT Enhanced

Mini-ACE are packaged in a 1.0-inch square ceramic flatpack package providing

footprint (with four pin differences) compatibility with previous generation Mini-ACE

terminals.

The BU-64743/64745 RT, and BU-64843/64845/64863 BC/RT/MT Mini-ACE Mark3

are packaged in a 0.890-inch square ceramic flatpack package. The BU-61740B RT,

and BU-61840B/61860B BC/RT/MT Micro-ACE and BU-

64840B/64843B/64860B/64863B BC/RT/MT Micro-ACE-TE are packaged in a 0.815-

inch square BGA package.

The BU-64843T BC/RT/MT Total-ACE (with integrated isolation transformers) is

packaged in a 1.100-inch x 0.600-inch rectangular, plastic BGA.

The Enhanced Mini-ACE series of hybrids provides software compatibility with the

previous generation Mini-ACE terminals, as well as software compatibility with the

older ACE series.

The Enhanced Mini-ACE RT provides complete multi-protocol support of MIL-STD-

1553A/B/McAir and STANAG 3838. All versions integrate dual transceiver; along with

protocol, host interface, memory management logic; and a minimum of 4K words of

RAM. In addition, the BU-61864/BU-61865/61860B/64863/64860B/64863B

BC/RT/MT terminals include 64K words of internal RAM, with built-in parity

checking.The Enhanced Mini-ACE series includes 5V or 3.3V, voltage source

transceivers for improved line driving capability, with options for MIL-STD-1760 and

McAir compatibility. As a means of reducing power consumption, there are versions

for which the logic is powered by 3.3V, rather than 5V. To provide further flexibility,

the Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or 20 MHz clock

inputs.

One of the salient new features of the Enhanced Mini-ACE is its enhanced bus

controller architecture. The Enhanced BC’s highly autonomous message sequence

control engine provides a means for offloading the host processor for implementing

minor and major frame timing control; asynchronous message insertion; data block

double buffering; bulk data transfers; and retry and bus switching strategy. For the

purpose of performing messaging to the host processor, the Enhanced BC mode

includes a General Purpose Queue, along with user-defined interrupts.

FUNCTIONAL OVERVIEW

Data Device Corporation 6 EMA User’s Guide (Volume 1)

The Enhanced Mini-ACE is the latest device group in the ACE family. The term

“enhanced” has also been used in earlier versions of the family to describe new

features introduced at each stage. For backward compatibility reasons, the same

terms and options have been maintained in the Enhanced Mini-ACE. The user will be

aware of Enhanced Mode, set by bit 15 of Configuration Register (CR) # 3 along with

the following optional features from earlier families:

Enhanced RT Memory Management CR#2 Bit #1

Enhanced RT Interrupt Handling CR#2 Bit #15

Enhanced Mode Code Handling CR#3 Bit #0

Enhanced Mode Enable CR#3 Bit #15

Expanded BC Control Word Enable CR#4 Bit #12

Plus for the latest devices:

Enhanced BC CR#6 Bit #15

Enhanced Time Tag Synchronization CR#7 Bit #2

Enhanced BC Watchdog Timer Enable CR#7 Bit #1

In many cases, the user may wish to enable most of these bits at initialization to have

all available features active.

A second major new feature of the Enhanced Mini-ACE is the incorporation of a fully

autonomous built-in self-test. This test provides comprehensive testing of the internal

protocol logic. A separate test verifies the operation of the internal RAM. Since the

self-tests are fully autonomous, they eliminate the need for the host to write and read

stimulus and response vectors.

The Enhanced Mini-ACE RT offers the same choices of single, double, and circular

buffering for individual subaddresses as the ACE and Mini-ACE (Plus). New

enhancements to the RT architecture include a global circular buffering option for

multiple (or all) receive subaddresses, a 50% rollover interrupt for circular buffers, an

interrupt status queue for logging up to 32 interrupt events, and an option to

automatically initialize to RT mode with the busy bit set

. The interrupt status queue

and 50% rollover interrupt features are also included as improvements to the

Enhanced Mini-ACE’s monitor architecture.

FUNCTIONAL OVERVIEW

Data Device Corporation 7 EMA User’s Guide (Volume 1)

To minimize board space and "glue" logic, the Enhanced Mini-ACE terminals provide

the same wide choice of host interface configurations as the ACE and Mini-ACE

(Plus). This includes support of shared RAM interfaces to 16-bit or 8-bit processors,

memory or port type interfaces, and multiplexed or non-multiplexed address/data

buses; plus a DMA interface configuration.

Hermetic, ceramic packaged, Enhanced Mini-ACE series terminals are available in

versions operating over the full military temperature range of -55 to +125°C

. Available

screened to MIL-PRF-38534C, these terminals are ideal for military and industrial

processor-to-1553 applications.

3.1 Transceivers

The transceivers in the Enhanced Mini-ACE series of terminals are fully monolithic,

requiring only a +5 or 3.3 volt power input

. The transmitters are voltage sources,

which provide improved line driving capability over current sources. This serves to

improve performance on long buses with many taps. The transmitters also offer an

option that satisfies the MIL-STD-1760 requirement for a minimum of 20 volts peak-

to-peak, transformer coupled output.

Besides eliminating the demand for an additional power supply, the use of a +5V or

3.3V -only transceivers requires the use of a step-up, rather than a step-down,

isolation transformer. This provides the advantage of higher terminal input impedance

than is possible for a 15 volt or 12 volt transmitter. As a result, there is a greater

margin for the input impedance test, mandated for the 1553 validation test

. This

characteristic allows for longer cable lengths between a system connector and the

isolation transformers of an embedded 1553 terminal. To provide compatibility to

McAir specs, the Enhanced Mini-ACE is available with an option for transmitters with

increased rise and fall times.

The receiver sections of the Enhanced Mini-ACE are fully compliant with MIL-STD-

1553B Notice 2 in terms of front end over voltage protection, threshold, common

mode rejection, and word error rate.

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