数字电路数码管倒计时VHDL源代码

以下是一个简单的数字电路数码管倒计时的VHDL源代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity countdown_timer is
    port(
        clk : in std_logic;
        reset : in std_logic;
        enable : in std_logic;
        output : out std_logic_vector(6 downto 0)
    );
end countdown_timer;

architecture rtl of countdown_timer is
    signal counter : unsigned(15 downto 0) := (others => '0');
    signal divisor : unsigned(15 downto 0) := (others => '0');
    signal tick : std_logic := '0';
    signal zero : std_logic := '0';

begin

    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                counter <= (others => '0');
                divisor <= (others => '0');
                tick <= '0';
                zero <= '0';
            else
                if enable = '1' then
                    divisor <= divisor + 1;
                    if divisor = 10000 then
                        divisor <= (others => '0');
                        counter <= counter - 1;
                        tick <= not tick;
                    end if;
                    if counter = 0 then
                        zero <= '1';
                    end if;
                end if;
            end if;
        end if;
    end process;

    output <= "1111110" when zero = '1' else
              "0110000" when counter = 0 else
              "0110111" when counter = 1 else
              "0010010" when counter = 2 else
              "1011011" when counter = 3 else
              "1001111" when counter = 4 else
              "1101101" when counter = 5 else
              "1111101" when counter = 6 else
              "0110011" when counter = 7 else
              "1111111" when counter = 8 else
              "1111011" when counter = 9 else
              "0000000";

end rtl;

该代码实现了一个简单的倒计时器，它将一个16位的计数器与一个定时器结合使用，以实现在时钟信号的帮助下递减一个数字，并将结果显示在七段数码管上。它还包括一个复位信号和一个使能信号，以控制计时器的行为。