四位全加器的verilog

module full_adder(
input a, b, cin,
output sum, cout
);

wire s1, s2;

// First half adder
half_adder ha1(a, b, s1, cout1);

// Second half adder
half_adder ha2(s1, cin, sum, s2);

// OR gate for carry out
or_gate og(cout1, s2, cout);

endmodule

module half_adder(
input a, b,
output sum, carry
);

// XOR gate for sum
xor_gate xg(a, b, sum);

// AND gate for carry
and_gate ag(a, b, carry);

endmodule

module xor_gate(
input a, b,
output c
);

assign c = a ^ b;

endmodule

module and_gate(
input a, b,
output c
);

assign c = a & b;

endmodule

module or_gate(
input a, b,
output c
);

assign c = a | b;

endmodule