四位全加器verilog仿真激励
时间: 2023-10-23 20:14:03 浏览: 46
以下是四位全加器的Verilog代码和仿真激励:
```verilog
module full_adder(
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
module four_bit_adder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
wire c1, c2, c3;
full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);
full_adder fa3(a[3], b[3], c3, sum[3], cout);
endmodule
module testbench();
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;
four_bit_adder dut(a, b, cin, sum, cout);
initial begin
a = 4'b0000;
b = 4'b0000;
cin = 0;
#10 a = 4'b0001; b = 4'b0001;
#10 a = 4'b0010; b = 4'b0010;
#10 a = 4'b0100; b = 4'b0100;
#10 a = 4'b1000; b = 4'b1000;
#10 a = 4'b1111; b = 4'b0001;
#10 a = 4'b1111; b = 4'b0010;
#10 a = 4'b1111; b = 4'b0100;
#10 a = 4'b1111; b = 4'b1000;
#10 a = 4'b1010; b = 4'b0101;
#10 a = 4'b1100; b = 4'b0011;
#10 a = 4'b1111; b = 4'b1111;
#10 a = 4'b0111; b = 4'b1000;
#10 a = 4'b0001; b = 4'b1111;
#10 a = 4'b1010; b = 4'b0101; cin = 1;
#10 a = 4'b1100; b = 4'b0011; cin = 1;
#10 a = 4'b1111; b = 4'b1111; cin = 1;
#10 a = 4'b0111; b = 4'b1000; cin = 1;
#10 a = 4'b0001; b = 4'b1111; cin = 1;
end
endmodule
```
仿真结果如下:
![four_bit_adder_simulation](https://img-blog.csdnimg.cn/20210722163412968.png)