module traffic_light( input clk, output reg n_s_red, output reg n_s_yellow, output reg n_s_green, output reg e_w_red, output reg e_w_yellow, output reg e_w_green); reg [2:0] state; // 定义状态 parameter S_NS_RED_EW_GREEN = 3'b000; parameter S_NS_YELLOW_EW_RED = 3'b001; parameter S_NS_GREEN_EW_RED = 3'b010; parameter S_NS_RED_EW_YELLOW = 3'b011; always @(posedge clk) begin case (state) S_NS_RED_EW_GREEN: begin n_s_red <= 1; n_s_yellow <= 0; n_s_green <= 0; e_w_red <= 0; e_w_yellow <= 1; e_w_green <= 0; #3 state <= S_NS_YELLOW_EW_RED; end S_NS_YELLOW_EW_RED: begin n_s_red <= 1; n_s_yellow <= 1; n_s_green <= 0; e_w_red <= 0; e_w_yellow <= 0; e_w_green <= 0; #1 state <= S_NS_GREEN_EW_RED; end S_NS_GREEN_EW_RED: begin n_s_red <= 0; n_s_yellow <= 0; n_s_green <= 1; e_w_red <= 1; e_w_yellow <= 0; e_w_green <= 0; #3 state <= S_NS_RED_EW_YELLOW; end S_NS_RED_EW_YELLOW: begin n_s_red <= 1; n_s_yellow <= 0; n_s_green <= 0; e_w_red <= 1; e_w_yellow <= 1; e_w_green <= 0; #1 state <= S_NS_RED_EW_GREEN; end endcase end // 初始状态 initial begin state <= S_NS_RED_EW_GREEN; endendmodule，为这段代码用veirlog语言编写仿真代码，在vivado上运行

以下是Traffic Light的仿真代码，可以在Vivado上运行：

module traffic_light_tb;

reg clk;
wire n_s_red, n_s_yellow, n_s_green, e_w_red, e_w_yellow, e_w_green;

traffic_light uut(
    .clk(clk),
    .n_s_red(n_s_red),
    .n_s_yellow(n_s_yellow),
    .n_s_green(n_s_green),
    .e_w_red(e_w_red),
    .e_w_yellow(e_w_yellow),
    .e_w_green(e_w_green)
);

initial begin
    clk = 0;
    #5;
    repeat(20) begin
        clk = ~clk;
        #5;
    end
    $finish;
end

endmodule

这里使用了一个简单的测试平台来测试Traffic Light模块。模块实例化为 `uut`，并将其6个输出连接到测试平台的6个wire。在 initial 块中，时钟信号 `clk` 被初始化为 0，并在每个时钟上升沿时翻转。整个仿真过程持续20个时钟周期，并在最后调用 $finish 命令结束仿真。