使用verlog HDL语言写出：用D触发器构成按循环码（000-001-011-111-101-100-000）规律工作的六进制同步计数器

module sync_counter(
input clk,
input reset,
output reg [2:0] count
);

reg [2:0] next_count;

// D触发器
always @(posedge clk, negedge reset) begin
if (!reset) begin
next_count <= 3'b000;
end else begin
case (count)
3'b000: next_count <= 3'b001;
3'b001: next_count <= 3'b011;
3'b011: next_count <= 3'b111;
3'b111: next_count <= 3'b101;
3'b101: next_count <= 3'b100;
3'b100: next_count <= 3'b000;
default: next_count <= 3'b000;
endcase
end
end

// 将下一个计数器的值赋给当前计数器
always @(posedge clk, negedge reset) begin
if (!reset) begin
count <= 3'b000;
end else begin
count <= next_count;
end
end

endmodule