3-8线译码器verilog实现代码和测试代码

以下是一个基本的3-8线译码器的Verilog实现代码和测试代码：

// 3-to-8 Decoder
module decoder_3to8(
    input [2:0] in, // 输入信号
    output reg [7:0] out // 输出信号
);

always @(*) begin
    case(in)
        3'b000: out = 8'h01;
        3'b001: out = 8'h02;
        3'b010: out = 8'h04;
        3'b011: out = 8'h08;
        3'b100: out = 8'h10;
        3'b101: out = 8'h20;
        3'b110: out = 8'h40;
        3'b111: out = 8'h80;
        default: out = 8'h00;
    endcase
end

endmodule

测试代码：

// 3-to-8 Decoder Test Bench
module decoder_3to8_tb;

reg [2:0] in;
wire [7:0] out;

decoder_3to8 dut(
    .in(in),
    .out(out)
);

initial begin
    $monitor("in=%b, out=%b", in, out);
    in = 3'b000;
    #10 in = 3'b001;
    #10 in = 3'b010;
    #10 in = 3'b011;
    #10 in = 3'b100;
    #10 in = 3'b101;
    #10 in = 3'b110;
    #10 in = 3'b111;
    #10 $finish;
end

endmodule

测试代码中，每10个时间单位改变一次输入信号，并在控制台上打印输入和输出信号。