实现一个按键控制的计数器，计数值在6位7段数码管上以十进制形式显示，按键1、2、3按一次可让结果分别加1，10，100，按复位键可使结果清零。 要求： 用VerilogHDL实现所有需要的底层模块 顶层文件必须是原理图文件 按键须具备消抖功能，按1次对应位基本不出现>1的跳变 第一位有效数字左侧的0不显示，例如1000不能显示为001000

实现的思路：

1. 实现按键模块，包括消抖功能；

2. 实现一个计数器模块，可以根据按键的输入进行加1、加10、加100、清零的操作；

3. 实现一个数码管驱动模块，将计数器的结果以十进制形式在七段数码管上显示；

4. 将以上模块进行连接，构建完整的电路。

以下是Verilog HDL代码实现:

1. 按键模块：

module button(input clk, input btn, output reg btn_out);

reg [23:0] btn_count;

always @(posedge clk) begin
    if(btn == 1'b0) begin
        if(btn_count == 24'hFFFFFF) // 防止溢出
            btn_count <= 24'hFFFFFF;
        else
            btn_count <= btn_count + 1;
    end
    else begin
        if(btn_count < 24'hFFFFFF && btn_count > 2'h0) // 消抖
            btn_out <= 1'b1;
        else
            btn_out <= 1'b0;
        btn_count <= 24'h0;
    end
end

endmodule

2. 计数器模块：

module counter(input clk, input [1:0] btn, input rst, output reg [5:0] count);

always @(posedge clk or posedge rst) begin
    if(rst)
        count <= 6'h0;
    else begin
        case(btn)
            2'h1: count <= count + 1;
            2'h2: count <= count + 10;
            2'h3: count <= count + 100;
        endcase
    end
end

endmodule

3. 数码管驱动模块：

module display(input clk, input [5:0] count, output reg [6:0] anode, output reg [6:0] seg);

wire [3:0] digit;

assign digit[0] = count[5:4];
assign digit[1] = count[3:2];
assign digit[2] = count[1:0];

reg [1:0] digit_sel;

always @(posedge clk) begin
    case(digit_sel)
        2'h0: begin
            anode = 7'b111_1110;
            case(digit[2])
                4'h0: seg = 7'b100_0000;
                4'h1: seg = 7'b111_1001;
                4'h2: seg = 7'b010_0100;
                4'h3: seg = 7'b011_0000;
                4'h4: seg = 7'b001_1001;
                4'h5: seg = 7'b001_0010;
                4'h6: seg = 7'b000_0010;
                4'h7: seg = 7'b111_1000;
                4'h8: seg = 7'b000_0000;
                4'h9: seg = 7'b001_0000;
                default: seg = 7'b111_1111;
            endcase
        end
        2'h1: begin
            anode = 7'b111_1101;
            case(digit[1])
                4'h0: seg = 7'b100_0000;
                4'h1: seg = 7'b111_1001;
                4'h2: seg = 7'b010_0100;
                4'h3: seg = 7'b011_0000;
                4'h4: seg = 7'b001_1001;
                4'h5: seg = 7'b001_0010;
                4'h6: seg = 7'b000_0010;
                4'h7: seg = 7'b111_1000;
                4'h8: seg = 7'b000_0000;
                4'h9: seg = 7'b001_0000;
                default: seg = 7'b111_1111;
            endcase
        end
        2'h2: begin
            anode = 7'b111_1011;
            case(digit[0])
                4'h0: seg = 7'b100_0000;
                4'h1: seg = 7'b111_1001;
                4'h2: seg = 7'b010_0100;
                4'h3: seg = 7'b011_0000;
                4'h4: seg = 7'b001_1001;
                4'h5: seg = 7'b001_0010;
                4'h6: seg = 7'b000_0010;
                4'h7: seg = 7'b111_1000;
                4'h8: seg = 7'b000_0000;
                4'h9: seg = 7'b001_0000;
                default: seg = 7'b111_1111;
            endcase
        end
    endcase
    digit_sel <= digit_sel + 1;
    if(digit_sel == 2'h3)
        digit_sel <= 2'h0;
end

endmodule

4. 顶层模块：

module top(input clk, input btn1, input btn2, input btn3, input rst, output reg [6:0] anode, output reg [6:0] seg);

wire btn1_out, btn2_out, btn3_out;
button button1(clk, btn1, btn1_out);
button button2(clk, btn2, btn2_out);
button button3(clk, btn3, btn3_out);

wire [5:0] count;
counter counter(clk, {btn3_out, btn2_out}, rst, count);

display display(clk, count, anode, seg);

endmodule

以上代码实现了一个按键控制的计数器，计数值在6位7段数码管上以十进制形式显示。