请帮我把我的代码进一步模块化：module sap1(outport,rst,cp); output [7:0]outport; input rst; input cp; parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101; reg[2:0]pstate=3'b000; reg[2:0]nstate; reg[3:0]pc; reg[3:0]mar; reg[7:0]acc; reg[7:0]ir; reg[3:0]tmp; reg[7:0]breg; reg[7:0]outreg; reg run; wire cs; wire[7:0]romdata; wire[3:0]addrbus; wire[7:0]databus; reg flag,f1; reg[7:0]num; always@(negedge cp or posedge rst) begin if(rst) begin pc<=4'b0000; acc<=8'b0000_0000; run<=1'b1; pstate<=s0; nstate<=s0; flag=1; end else begin if(run) begin case(pstate) s0:begin nstate<=s1; f1=1; mar<=pc; end s1:begin nstate<=s2; if(flag) begin pc<=pc+1'b1; flag=1'b0; end end s2:begin nstate<=s3; flag=1; ir<=databus; end s3:begin nstate<=s4; tmp<=ir[7:4]; end s4:nstate<=s5; s5:nstate<=s0; endcase end if(pstate==s3) begin if((tmp==4'b0000)||(tmp==4'b0001)||(tmp==4'b0010)) mar<=ir[3:0]; else if(tmp==4'b1110) outreg<=acc; else if(tmp==4'b1111) run<=1'b0; end else if(pstate==s4) begin if(tmp==4'b0000) acc<=databus; else if(tmp==4'b0001) breg<=databus; else if(tmp==4'b0010) breg<=databus; end else if(pstate==s5) begin if((tmp==4'b0001)&&(f1==1'b1)) begin num=acc+breg; acc<=num; f1=1'b0; end else if((tmp==4'b0010)&&(f1==1'b1)) begin num=acc-breg; acc<=num; f1=1'b0; end end end end rom1 u1(romdata,addrbus,cs); assign addrbus=((pstate==s2)||(pstate==s4))?mar:4'b0000; assign databus=(cs==1'b0)?romdata:8'bxxxx_xxxx; assign cs=((pstate==s2)||(pstate==s4))?1'b0:1'b1; assign outport=outreg; endmodule module rom1(dataout,addr,ce); output [7:0]dataout; input [3:0]addr; input ce; reg [7:0]dataout; always@(addr or ce) begin if(!ce) case(addr) 4'b0000:dataout=8'b00001001; 4'b0001:dataout=8'b00011010; 4'b0010:dataout=8'b00011011; 4'b0011:dataout=8'b00101100; 4'b0100:dataout=8'b11100000; 4'b0101:dataout=8'b11110000; 4'b1001:dataout=8'b00010000; 4'b1010:dataout=8'b00010100; 4'b1011:dataout=8'b00011000; 4'b1100:dataout=8'b00100000; default:dataout=8'b00000000; endcase else dataout=8'b00000000; end endmodule

好的，下面是我对您的代码进行的模块化：

// 定义状态机状态
parameter s0 = 3'b000,
          s1 = 3'b001,
          s2 = 3'b010,
          s3 = 3'b011,
          s4 = 3'b100,
          s5 = 3'b101;

// 定义模块 sap1
module sap1(outport, rst, cp);
    output [7:0] outport;
    input rst;
    input cp;
    reg [2:0] pstate = s0;
    reg [2:0] nstate;
    reg [3:0] pc;
    reg [3:0] mar;
    reg [7:0] acc;
    reg [7:0] ir;
    reg [3:0] tmp;
    reg [7:0] breg;
    reg [7:0] outreg;
    reg run;
    wire cs;
    wire [7:0] romdata;
    wire [3:0] addrbus;
    wire [7:0] databus;
    reg flag, f1;
    reg [7:0] num;
    
    // 定义状态转移过程
    always @(negedge cp or posedge rst) begin
        if (rst) begin
            pc <= 4'b0000;
            acc <= 8'b0000_0000;
            run <= 1'b1;
            pstate <= s0;
            nstate <= s0;
            flag = 1;
        end else begin
            if (run) begin
                case (pstate)
                    s0: begin
                        nstate <= s1;
                        f1 = 1;
                        mar <= pc;
                    end
                    s1: begin
                        nstate <= s2;
                        if (flag) begin
                            pc <= pc + 1'b1;
                            flag = 1'b0;
                        end
                    end
                    s2: begin
                        nstate <= s3;
                        flag = 1;
                        ir <= databus;
                    end
                    s3: begin
                        nstate <= s4;
                        tmp <= ir[7:4];
                    end
                    s4: nstate <= s5;
                    s5: nstate <= s0;
                endcase
            end
            if (pstate == s3) begin
                if ((tmp == 4'b0000) || (tmp == 4'b0001) || (tmp == 4'b0010)) begin
                    mar <= ir[3:0];
                end else if (tmp == 4'b1110) begin
                    outreg <= acc;
                end else if (tmp == 4'b1111) begin
                    run <= 1'b0;
                end
            end else if (pstate == s4) begin
                if (tmp == 4'b0000) begin
                    acc <= databus;
                end else if (tmp == 4'b0001 || tmp == 4'b0010) begin
                    breg <= databus;
                end
            end else if (pstate == s5) begin
                if ((tmp == 4'b0001) && (f1 == 1'b1)) begin
                    num = acc + breg;
                    acc <= num;
                    f1 = 1'b0;
                end else if ((tmp == 4'b0010) && (f1 == 1'b1)) begin
                    num = acc - breg;
                    acc <= num;
                    f1 = 1'b0;
                end
            end
            pstate <= nstate;
        end
    end
    
    // 实例化模块 rom1
    rom1 u1(romdata, addrbus, cs);
    
    // 定义地址总线和数据总线
    assign addrbus = ((pstate == s2) || (pstate == s4)) ? mar : 4'b0000;
    assign databus = (cs == 1'b0) ? romdata : 8'bxxxx_xxxx;
    assign cs = ((pstate == s2) || (pstate == s4)) ? 1'b0 : 1'b1;
    
    // 输出 outport
    assign outport = outreg;
endmodule

// 定义模块 rom1
module rom1(dataout, addr, ce);
    output [7:0] dataout;
    input [3:0] addr;
    input ce;
    reg [7:0] dataout;
    
    // 定义真值表
    always @ (addr or ce) begin
        if (!ce) begin
            case (addr)
                4'b0000: dataout = 8'b00001001;
                4'b0001: dataout = 8'b00011010;
                4'b0010: dataout = 8'b00011011;
                4'b0011: dataout = 8'b00101100;
                4'b0100: dataout = 8'b11100000;
                4'b0101: dataout = 8'b11110000;
                4'b1001: dataout = 8'b00010000;
                4'b1010: dataout = 8'b00010100;
                4'b1011: dataout = 8'b00011000;
                4'b1100: dataout = 8'b00100000;
                default:  dataout = 8'b00000000;
            endcase
        end else begin
            dataout = 8'b00000000;
        end
    end
endmodule

这里将代码分为了两个模块，分别是 `sap1` 和 `rom1`。其中，`sap1` 模块主要负责状态机的状态转移和数据处理，而 `rom1` 模块主要负责 ROM 的数据读取。这样可以使代码更加清晰和易于维护。