entity div_10 is Port ( clk1 : in std_logic; rst1 : in std_logic; out1: out std_logic ); end div_10; architecture a of div_10 is signal count: integer range 0 to 9; signal out2: std_logic; begin process (clk1, rst1) begin if (rst1='1') then count <= 0; out1 <= '0'; out2 <= '0'; elsif (rising_edge(clk1)) then if (count = 9) then count <= 0; out2 <= not out2; else count <= count + 1; end if; if (out2 = '0') then out1 <= '1'; else out1 <= '0'; end if; end if; end process; end a;修改VHDL代码的分频系数为50和3，分别给出

修改后的代码如下：

分频系数为50：

entity div_50 is
Port (
clk1 : in std_logic;
rst1 : in std_logic;
out1 : out std_logic
);
end div_50;

architecture a of div_50 is
signal count : integer range 0 to 49;
signal out2 : std_logic;
begin
process (clk1, rst1)
begin
if (rst1 = '1') then
count <= 0;
out1 <= '0';
out2 <= '0';
elsif (rising_edge(clk1)) then
if (count = 49) then
count <= 0;
out2 <= not out2;
else
count <= count + 1;
end if;
if (out2 = '0') then
out1 <= '1';
else
out1 <= '0';
end if;
end if;
end process;
end a;

分频系数为3：

entity div_3 is
Port (
clk1 : in std_logic;
rst1 : in std_logic;
out1 : out std_logic
);
end div_3;

architecture a of div_3 is
signal count : integer range 0 to 2;
signal out2 : std_logic;
begin
process (clk1, rst1)
begin
if (rst1 = '1') then
count <= 0;
out1 <= '0';
out2 <= '0';
elsif (rising_edge(clk1)) then
if (count = 2) then
count <= 0;
out2 <= not out2;
else
count <= count + 1;
end if;
if (out2 = '0') then
out1 <= '1';
else
out1 <= '0';
end if;
end if;
end process;
end a;