begin c_state <= #1 start_c; scl_oen <= #1 1'b1; // set SCL high sda_oen <= #1 1'b1; // keep SDA high sda_chk <= #1 1'b0; // don't check SDA output end
时间: 2024-02-10 21:35:04 浏览: 25
这段代码是一个状态机中的一个状态,当状态机进入该状态时,会执行 begin 和 end 之间的操作。其中,c_state 是状态机的状态寄存器,start_c 是状态机的下一个状态,scl_oen、sda_oen 和 sda_chk 分别是控制 SCL 和 SDA 信号的输出端口和输入端口的信号。在这个状态中,首先将状态机的状态寄存器 c_state 赋值为 start_c,然后将 scl_oen 信号置为高电平,即输出 SCL 信号为高电平;将 sda_oen 信号置为高电平,即输出 SDA 信号为高电平;将 sda_chk 信号置为低电平,即不检测 SDA 信号的输出。这个状态的目的是在开始传输之前,将 SCL 和 SDA 信号都拉高,并为之后的状态做好准备。
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always @(posedge clk or negedge nReset) if (~nReset) begin cnt <= #1 16'h0; clk_en <= #1 1'b1; end else if (rst || ~|cnt || !ena || scl_sync) begin cnt <= #1 clk_cnt; clk_en <= #1 1'b1; end else if (slave_wait) begin cnt <= #1 cnt; clk_en <= #1 1'b0; end else begin cnt <= #1 cnt - 16'h1; clk_en <= #1 1'b0; end
这是一个 Verilog 代码段,它描述了一个时钟计数器。这个计数器会在时钟上升沿或下降沿触发,同时也会在 nReset 信号为低电平时进行重置。当重置信号为低电平时,计数器会被清零,并启用时钟。如果 rst 信号为高电平,或者计数器的值为零,或者使能信号为低电平,或者 scl_sync 信号为高电平,计数器也会被重置并启用时钟。如果 slave_wait 信号为高电平,则计数器会保持不变,时钟禁用。否则,计数器会每次递减 1,时钟禁用。
改写一下这段代码,使得寄存器地址支持16bit读写,现在这段是只支持8bit读写://FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase
以下是修改后的代码,支持16bit读写:
//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[15:2])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[15:2])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase
修改的内容:
1. 在设备地址检测&触发状态中,将设备地址的位数扩展到16位,即将sft[7:1]修改为sft[15:2]。
2. 在写寄存器地址检测&触发状态中,同样将地址的位数扩展到16位。
3. 在读寄存器数据状态和写寄存器数据状态中,没有需要修改的地方。
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