module project( clk, rst, ENA, init_num, SEL, SEG ); input clk; input rst; input ENA; input [3:0]init_num; output [1:0]SEL; output [7:0]SEG; reg clk_1Hz; reg [27:0]div_cnt; always@(posedge clk or negedge rst) if (!rst) div_cnt <= 0; else if (div_cnt >= 28'd99999999) // 1Hz——99999999 div_cnt <= 0; else div_cnt <= div_cnt + 1'b1; always@(posedge clk or negedge rst) if (!rst) clk_1Hz <= 0; else if (div_cnt == 28'd99999999) // 1Hz--99999999 clk_1Hz <= 1'b1; else clk_1Hz <= 0; reg [3:0]disp_num = 0; reg reverse = 0; always@(posedge clk_1Hz or negedge rst) begin if (!rst) disp_num <= init_num; else if (!ENA) ; else if (disp_num == 15) begin //正向计数到15 reverse <= 1; disp_num <= disp_num - 1; end else if (disp_num == 0 && reverse) begin //反向计数到0 reverse <= 0; disp_num <= disp_num + 1; end else if (!reverse) disp_num <= disp_num + 1; else if (reverse) disp_num <= disp_num - 1; end smg_disp_1 u1( .Clk(clk), .Reset_n(rst), .Disp_Data(disp_num), .SEL(SEL), .SEG(SEG) ); endmodule给代码进行注释

下面是代码的注释：

module project(
    clk,    //时钟信号
    rst,    //同步复位信号
    ENA,    //使能控制信号
    init_num,   //预置数
    SEL,    //数码管位选信号
    SEG     //数码管段选信号
);
    input clk;  //时钟信号
    input rst;  //同步复位信号
    input ENA;  //使能控制信号
    input [3:0] init_num;   //预置数，4位二进制数
    output [1:0] SEL;  //数码管位选信号
    output [7:0] SEG;  //数码管段选信号

    reg clk_1Hz;   //1Hz的时钟信号
    reg [27:0] div_cnt; //时钟信号的分频计数器

    always@(posedge clk or negedge rst)   //时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            div_cnt <= 0;   //分频计数器清零
        else if (div_cnt >= 28'd99999999) //分频计数器计数到99999999
            div_cnt <= 0;   //分频计数器清零
        else
            div_cnt <= div_cnt + 1'b1;   //分频计数器加1

    always@(posedge clk or negedge rst)   //时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            clk_1Hz <= 0;   //1Hz的时钟信号为低电平
        else if (div_cnt == 28'd99999999) //分频计数器计数到99999999
            clk_1Hz <= 1'b1;    //1Hz的时钟信号为高电平
        else
            clk_1Hz <= 0;   //1Hz的时钟信号为低电平

    reg [3:0] disp_num = 0; //计数器的输出数值，默认为0
    reg reverse = 0;    //计数器的计数方向，默认为正向计数

    always@(posedge clk_1Hz or negedge rst) begin   //1Hz的时钟信号上升沿或同步复位信号下降沿触发
        if (!rst)   //同步复位信号为低电平
            disp_num <= init_num;   //计数器的输出数值为预置数
        else if (!ENA) //使能控制信号为低电平
            ;   //计数器不进行计数
        else if (disp_num == 15) begin   //正向计数到15
            reverse <= 1;   //计数方向反转
            disp_num <= disp_num - 1;   //计数器减1
        end
        else if (disp_num == 0 && reverse) begin //反向计数到0
            reverse <= 0;   //计数方向反转
            disp_num <= disp_num + 1;   //计数器加1
        end
        else if (!reverse) //正向计数
            disp_num <= disp_num + 1;   //计数器加1
        else if (reverse)  //反向计数
            disp_num <= disp_num - 1;   //计数器减1
    end

    smg_disp_1 u1(  //数码管驱动模块
        .Clk(clk), //时钟信号
        .Reset_n(rst),  //同步复位信号
        .Disp_Data(disp_num),   //计数器的输出数值
        .SEL(SEL),  //数码管位选信号
        .SEG(SEG)   //数码管段选信号
    );
endmodule