`timescale 1ns / 1ps module digital( input clk , input rstn , input [3:0] data1, input [3:0] data2, input [3:0] data3, input [3:0] data4, output reg [7:0] seg , output reg [3:0] sel ); reg [15:0]cn1; reg clk1k; always@(posedge clk or negedge rstn) //分频 begin if(!rstn)begin cn1<=0; clk1k<=0; end else if(cn1>=24999)begin //累积到24999 clk1k<=!clk1k; cn1<=0; end else begin cn1<=cn1+1; end end reg [3:0] tub; reg [2:0] state; always@(posedge clk1k or negedge rstn) begin if(!rstn)begin tub <= 0; state <= 0; sel <= 0; end else begin case(state) 0:begin tub<=data1;sel<=4'b0111;state<=1;end 1:begin tub<=data2;sel<=4'b1110;state<=2;end 2:begin tub<=data3;sel<=4'b1101;state<=3;end 3:begin tub<=data4;sel<=4'b1011;state<=0;end default:state<=0; endcase end end always@(posedge clk1k or negedge rstn) if(!rstn) seg<=8'b0000_0011; else case(tub) // 0-9 4'b0000 : seg <= 8'b0000_0011; 4'b0001 : seg <= 8'b1001_1111; 4'b0010 : seg <= 8'b0010_0101; 4'b0011 : seg <= 8'b0000_1101; 4'b0100 : seg <= 8'b1001_1001; 4'b0101 : seg <= 8'b0100_1001; 4'b0110 : seg <= 8'b0100_0001; 4'b0111 : seg <= 8'b0001_1111; 4'b1000 : seg <= 8'b0000_0001; 4'b1001 : seg <= 8'b0000_1001; default:seg<=8'b0000_0011; endcase endmodule上述代码是当输入数据为0x1346时数码管正确显示0x1346，请告诉我怎么将它修改为当输入数字为十进制数数码管能正确显示数字的代码。例如输入为十进制数4567，数码管正确显示4567

修改后的代码如下：

`timescale 1ns / 1ps 
module digital( 
    input            clk  ,
    input            rstn ,
    input      [15:0] data,
    output reg [7:0] seg  ,
    output reg [3:0] sel    
);

reg [15:0]cn1; 
reg clk1k; 
reg [3:0] tub; 
reg [2:0] state;

always@(posedge clk or negedge rstn)
begin 
    if(!rstn)
    begin 
        cn1<=0; 
        clk1k<=0; 
    end 
    else if(cn1>=24999)
    begin
        clk1k<=!clk1k; 
        cn1<=0; 
    end 
    else
    begin 
        cn1<=cn1+1; 
    end 
end 

always@(posedge clk1k or negedge rstn) 
begin 
    if(!rstn)
    begin 
        tub   <= 0; 
        state <= 0; 
        sel   <= 0; 
    end 
    else
    begin 
        case(state) 
            0:begin tub<=data[3:0];sel<=4'b0111;state<=1;end 
            1:begin tub<=data[7:4];sel<=4'b1110;state<=2;end 
            2:begin tub<=data[11:8];sel<=4'b1101;state<=3;end 
            3:begin tub<=data[15:12];sel<=4'b1011;state<=0;end 
            default:state<=0; 
        endcase 
    end 
end 

always@(posedge clk1k or negedge rstn)
begin 
    if(!rstn) 
    begin
        seg<=8'b0000_0011; 
    end 
    else
    begin
        case(tub) 
            4'b0000 : seg <= 8'b0000_0011; 
            4'b0001 : seg <= 8'b1001_1111; 
            4'b0010 : seg <= 8'b0010_0101; 
            4'b0011 : seg <= 8'b0000_1101; 
            4'b0100 : seg <= 8'b1001_1001; 
            4'b0101 : seg <= 8'b0100_1001; 
            4'b0110 : seg <= 8'b0100_0001; 
            4'b0111 : seg <= 8'b0001_1111; 
            4'b1000 : seg <= 8'b0000_0001; 
            4'b1001 : seg <= 8'b0000_1001; 
            default:seg<=8'b0000_0011; 
        endcase 
    end 
end 

endmodule

上述代码将输入数据改为16位，其中高12位为0，低4位为输入的十进制数。在状态机中每次取出4位，分别对应输入数字的千位、百位、十位和个位，并用数码管显示出来。