module ram_write ( input wire sys_clk , input wire sys_rst_n , input wire cnt_rcd, input wire [7:0] seg_cnt_data0 , input wire [7:0] seg_cnt_data1 , input wire [7:0] seg_cnt_data2 , input wire [7:0] seg_cnt_data3 , input wire [7:0] seg_cnt_data4 , input wire [7:0] seg_cnt_data5 , output reg [4:0] addr, output reg write_en , output reg [7:0] data_in ); reg [3:0] bite ; reg [3:0] times=0; always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin write_en <= 1'b0 ; end else if (cnt_rcd) begin write_en <= 1'b1; times <= times + 1; end else begin write_en <= 1'b0; end end always @(posedge sys_clk or negedge sys_rst_n) if(!sys_rst_n) begin bite <='d0; addr <='d0; data_in <='d0; end else if(write_en) begin case(bite) 'd0: begin addr <= 2'd0+6times ; data_in<= seg_cnt_data0 ; bite<=bite + 1 ; end 'd1: begin addr <= 2'd1+6times ; data_in<= seg_cnt_data1; bite<=bite + 1 ; end 'd2: begin addr <= 2'd2+6times ; data_in<= seg_cnt_data2 ; bite<=bite + 1 ; end 'd3: begin addr <= 2'd3+6times ; data_in<= seg_cnt_data3 ; bite<=bite + 1 ; end 'd4: begin addr <= 2'd4+6times ; data_in<= seg_cnt_data4 ; bite<=bite + 1 ; end 'd5: begin addr <= 2'd5+6times ; data_in<= seg_cnt_data5 ; bite<=bite + 1 ; end default: ; endcase end endmodule修改代码

根据您提供的代码，我发现在更新 `addr` 时，使用的是 `6times`，这里应该是 `6*times`，需要在乘法符号前面加上 `*`，以正确计算地址。请尝试修改如下代码：

module ram_write (
    input wire sys_clk,
    input wire sys_rst_n,
    input wire cnt_rcd,
    input wire [7:0] seg_cnt_data0,
    input wire [7:0] seg_cnt_data1,
    input wire [7:0] seg_cnt_data2,
    input wire [7:0] seg_cnt_data3,
    input wire [7:0] seg_cnt_data4,
    input wire [7:0] seg_cnt_data5,
    output reg [4:0] addr,
    output reg write_en,
    output reg [7:0] data_in
);

    reg [3:0] bite;
    reg [3:0] times = 0;

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            write_en <= 1'b0;
        end else if (cnt_rcd) begin
            write_en <= 1'b1;
            times <= times + 1;
        end else begin
            write_en <= 1'b0;
        end
    end

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            bite <= 'd0;
            addr <= 'd0;
            data_in <= 'd0;
        end else if (write_en) begin
            case (bite)
                'd0: begin
                    addr <= 2'd0 + 6 * times;
                    data_in <= seg_cnt_data0;
                    bite <= bite + 1;
                end
                'd1: begin
                    addr <= 2'd1 + 6 * times;
                    data_in <= seg_cnt_data1;
                    bite <= bite + 1;
                end
                'd2: begin
                    addr <= 2'd2 + 6 * times;
                    data_in <= seg_cnt_data2;
                    bite <= bite + 1;
                end
                'd3: begin
                    addr <= 2'd3 + 6 * times;
                    data_in <= seg_cnt_data3;
                    bite <= bite + 1;
                end
                'd4: begin
                    addr <= 2'd4 + 6 * times;
                    data_in <= seg_cnt_data4;
                    bite <= bite + 1;
                end
                'd5: begin
                    addr <= 2'd5 + 6 * times;
                    data_in <= seg_cnt_data5;
                    bite <= bite + 1;
                end
                default: ;
            endcase
        end
    end

endmodule

请尝试使用上述代码，看看问题是否得到解决。