请用verilog实现一个4bit加法器

module adder_4bit(A, B, Cin, S, Cout);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;

wire [3:0] sum;
wire c1, c2, c3;

assign sum[0] = A[0] ^ B[0] ^ Cin;
assign c1 = (A[0] & B[0]) | (A[0] & Cin) | (B[0] & Cin);
assign sum[1] = A[1] ^ B[1] ^ c1;
assign c2 = (A[1] & B[1]) | (A[1] & c1) | (B[1] & c1);
assign sum[2] = A[2] ^ B[2] ^ c2;
assign c3 = (A[2] & B[2]) | (A[2] & c2) | (B[2] & c2);
assign sum[3] = A[3] ^ B[3] ^ c3;
assign Cout = (A[3] & B[3]) | (A[3] & c3) | (B[3] & c3);

assign S = sum;

endmodule

这是一个简单的4位加法器，使用三个全加器组成。每个全加器有两个输入位和一个进位位。