四人抢答器verilog

以下是一个简单的四人抢答器的Verilog代码：

module buzzer(input clk, input rst, input [3:0] in, output reg [3:0] out);

reg [3:0] buzzer;

always @(posedge clk) begin
    if (rst) begin
        buzzer <= 4'b0000;
    end else if (in == 4'b0001) begin
        buzzer <= 4'b0001;
    end else if (in == 4'b0010) begin
        buzzer <= 4'b0010;
    end else if (in == 4'b0100) begin
        buzzer <= 4'b0100;
    end else if (in == 4'b1000) begin
        buzzer <= 4'b1000;
    end
end

always @(posedge clk) begin
    if (rst) begin
        out <= 4'b0000;
    end else if (buzzer == 4'b0001) begin
        out <= 4'b0001;
    end else if (buzzer == 4'b0010) begin
        out <= 4'b0010;
    end else if (buzzer == 4'b0100) begin
        out <= 4'b0100;
    end else if (buzzer == 4'b1000) begin
        out <= 4'b1000;
    end
end

endmodule

这个代码使用了两个always块。第一个always块根据输入in判断哪个人先按下了抢答器，然后将其对应的值存入buzzer寄存器中。第二个always块根据buzzer寄存器中存储的值将对应的输出信号送出。当rst信号为1时，抢答器重置并将所有信号置为0。