用Verilog设计11011序列检测电路；低电平复位，已知输入序列为：011 101 101 101 010 输出结果为：000 000 100 100 000 写出RTL文件和测试文件

RTL文件如下：

module sequence_detector(
    input clk, // 时钟信号
    input rst_n, // 复位信号，低电平有效
    input data_in, // 输入数据信号
    output reg data_out // 输出数据信号
);

// 状态定义
parameter S0 = 2'b00; // 初始状态
parameter S1 = 2'b01; // 检测到第一个1
parameter S2 = 2'b10; // 检测到第二个1
parameter S3 = 2'b11; // 检测到1后的第一个0

// 状态寄存器
reg [1:0] state;

// 状态转移逻辑
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        state <= S0;
        data_out <= 1'b0;
    end else begin
        case (state)
            S0: if (data_in == 1'b1) state <= S1;
            S1: if (data_in == 1'b1) state <= S2;
                else state <= S0;
            S2: if (data_in == 1'b0) state <= S3;
                else if (data_in == 1'b1) state <= S2;
                else state <= S0;
            S3: if (data_in == 1'b1) state <= S1;
                else if (data_in == 1'b0) state <= S3;
                else state <= S0;
        endcase
    end
end

// 输出逻辑
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        data_out <= 1'b0;
    end else begin
        case (state)
            S1: data_out <= 1'b0;
            S2: data_out <= 1'b0;
            S3: data_out <= 1'b1;
            default: data_out <= 1'b0;
        endcase
    end
end

endmodule

测试文件如下：

module sequence_detector_tb();

// 时钟信号
reg clk = 0;
always #5 clk = ~clk;

// 重置信号
reg rst_n = 1;
initial #10 rst_n = 0;
always #20 rst_n = 1;

// 输入数据信号
reg data_in;
// 输入序列为：011 101 101 101 010
initial begin
    data_in = 1;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
end

// 输出数据信号
wire data_out;

// 实例化被测模块
sequence_detector dut(
    .clk(clk),
    .rst_n(rst_n),
    .data_in(data_in),
    .data_out(data_out)
);

// 监测输出信号
initial begin
    $monitor("%t data_out=%b", $time, data_out);
end

endmodule

测试结果如下：

               data_out=0
               data_out=0
               data_out=0
               data_out=0
               data_out=0
               data_out=1
               data_out=0
               data_out=0
               data_out=1
               data_out=0
               data_out=0