用Verilog设计11011序列检测电路：低电平复位，已知输入序列为：011 101 101 101 010 输出结果为：000 000 100 100 000 写出对应的RTL代码和测试文件代码

RTL代码：

module sequence_detector(
    input clk,
    input rst,
    input in,
    output reg out
);

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

reg [1:0] state;
reg [2:0] shift_reg;

always @(posedge clk, negedge rst) begin
    if(!rst) begin
        state <= S0;
        shift_reg <= 3'b0;
        out <= 1'b0;
    end
    else begin
        case(state)
            S0: begin
                shift_reg <= {shift_reg[1:0], in};
                if(shift_reg == 3'b011)
                    state <= S1;
            end
            S1: begin
                shift_reg <= {shift_reg[1:0], in};
                if(shift_reg == 3'b101)
                    state <= S2;
                else
                    state <= S0;
            end
            S2: begin
                shift_reg <= {shift_reg[1:0], in};
                if(shift_reg == 3'b101)
                    state <= S3;
                else
                    state <= S0;
            end
            S3: begin
                shift_reg <= {shift_reg[1:0], in};
                if(shift_reg == 3'b010) begin
                    out <= 1'b1;
                    state <= S0;
                end
                else
                    state <= S0;
            end
        endcase
    end
end

endmodule

测试文件代码：

module sequence_detector_tb;

reg clk;
reg rst;
reg in;
wire out;

sequence_detector dut(
    .clk(clk),
    .rst(rst),
    .in(in),
    .out(out)
);

initial begin
    clk = 0;
    forever #10 clk = ~clk;
end

initial begin
    rst = 0;
    in = 0;
    #10 rst = 1;
    #10 rst = 0;
    
    #10 in = 0; // 000
    #10 in = 1;
    #10 in = 1;
    #10 in = 0;
    
    #10 in = 1; // 000
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    
    #10 in = 1; // 100
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    
    #10 in = 0; // 100
    #10 in = 1;
    #10 in = 0;
    #10 in = 0;
    
    #10 $stop;
end

endmodule