用Verilog设计11011序列检测电路；低电平复位，已知输入序列为：011 101 101 101 010 输出结果为：000 000 100 100 000 RTL文件和tb测试文件

以下是Verilog设计11011序列检测电路的RTL代码:

module seq_detector (
    input clk, reset, 
    input data_in,
    output reg data_out
);

parameter S0 = 2'b00; // Start
parameter S1 = 2'b01; // 1
parameter S2 = 2'b10; // 11
parameter S3 = 2'b11; // 110
parameter S4 = 2'b100; // 1101

reg [1:0] state;

always @(posedge clk or negedge reset) begin
    if (reset == 0) begin
        state <= S0;
        data_out <= 0;
    end else begin
        case(state)
            S0: if (data_in == 1) state <= S0; else state <= S1;
            S1: if (data_in == 1) state <= S2; else state <= S1;
            S2: if (data_in == 1) state <= S3; else state <= S1;
            S3: if (data_in == 1) state <= S4; else state <= S1;
            S4: if (data_in == 1) begin
                    state <= S0;
                    data_out <= 1;
                end else state <= S1;
        endcase
    end
end

endmodule

以下是对应的测试文件tb的代码：

module tb_seq_detector;

reg clk, reset, data_in;
wire data_out;

seq_detector dut (
    .clk(clk),
    .reset(reset),
    .data_in(data_in),
    .data_out(data_out)
);

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    reset = 0;
    #10;
    reset = 1;
    #10;
    reset = 0;
end

initial begin
    data_in = 0;
    #10;
    for (int i=0; i<3; i++) begin
        data_in = 0;
        #10;
        data_in = 1;
        #10;
        data_in = 1;
        #10;
        data_in = 0;
        #10;
        data_in = 1;
        #10;
    end
end

endmodule

在这个测试文件中，我们首先将reset信号拉低，然后等待一段时间后将其拉高，以使电路初始化。然后我们将输入数据按照题目所给出的序列输入，最终得到的data_out信号应该与题目所给出的输出序列相同。