编写一段输入信号为5位二进制数，输出信号为8位BCD码的verilog程序。包括设计代码和测试代码

下面是一个完整的Verilog程序，包括设计代码和测试代码，实现将5位二进制数转换为8位BCD码：

设计代码：

module bin_to_bcd(
  input [4:0] bin_input,
  output reg [7:0] bcd_output
);

  always @(*) begin
    case(bin_input)
      5'b00000: bcd_output = 8'b00000000;
      5'b00001: bcd_output = 8'b00000001;
      5'b00010: bcd_output = 8'b00000010;
      5'b00011: bcd_output = 8'b00000011;
      5'b00100: bcd_output = 8'b00000100;
      5'b00101: bcd_output = 8'b00000101;
      5'b00110: bcd_output = 8'b00000110;
      5'b00111: bcd_output = 8'b00000111;
      5'b01000: bcd_output = 8'b00001000;
      5'b01001: bcd_output = 8'b00001001;
      5'b01010: bcd_output = 8'b00010000;
      5'b01011: bcd_output = 8'b00010001;
      5'b01100: bcd_output = 8'b00010010;
      5'b01101: bcd_output = 8'b00010011;
      5'b01110: bcd_output = 8'b00010100;
      5'b01111: bcd_output = 8'b00010101;
      5'b10000: bcd_output = 8'b00100000;
      5'b10001: bcd_output = 8'b00100001;
      5'b10010: bcd_output = 8'b00100010;
      5'b10011: bcd_output = 8'b00100011;
      5'b10100: bcd_output = 8'b00100100;
      5'b10101: bcd_output = 8'b00100101;
      5'b10110: bcd_output = 8'b00100110;
      5'b10111: bcd_output = 8'b00100111;
      5'b11000: bcd_output = 8'b00101000;
      5'b11001: bcd_output = 8'b00101001;
      5'b11010: bcd_output = 8'b00110000;
      5'b11011: bcd_output = 8'b00110001;
      5'b11100: bcd_output = 8'b00110010;
      5'b11101: bcd_output = 8'b00110011;
      5'b11110: bcd_output = 8'b00110100;
      5'b11111: bcd_output = 8'b00110101;
      default: bcd_output = 8'b00000000;
    endcase
  end

endmodule

测试代码：

module bin_to_bcd_tb;

  reg [4:0] bin_input;
  wire [7:0] bcd_output;

  bin_to_bcd dut(
    .bin_input(bin_input),
    .bcd_output(bcd_output)
  );

  initial begin
    $monitor("bin_input = %b, bcd_output = %b", bin_input, bcd_output);
    #5 bin_input = 5'b00001;
    #5 bin_input = 5'b00010;
    #5 bin_input = 5'b00011;
    #5 bin_input = 5'b00100;
    #5 bin_input = 5'b00101;
    #5 bin_input = 5'b00110;
    #5 bin_input = 5'b00111;
    #5 bin_input = 5'b01000;
    #5 bin_input = 5'b01001;
    #5 bin_input = 5'b01010;
    #5 bin_input = 5'b01011;
    #5 bin_input = 5'b01100;
    #5 bin_input = 5'b01101;
    #5 bin_input = 5'b01110;
    #5 bin_input = 5'b01111;
    #5 bin_input = 5'b10000;
    #5 bin_input = 5'b10001;
    #5 bin_input = 5'b10010;
    #5 bin_input = 5'b10011;
    #5 bin_input = 5'b10100;
    #5 bin_input = 5'b10101;
    #5 bin_input = 5'b10110;
    #5 bin_input = 5'b10111;
    #5 bin_input = 5'b11000;
    #5 bin_input = 5'b11001;
    #5 bin_input = 5'b11010;
    #5 bin_input = 5'b11011;
    #5 bin_input = 5'b11100;
    #5 bin_input = 5'b11101;
    #5 bin_input = 5'b11110;
    #5 bin_input = 5'b11111;
    #5 $finish;
  end

endmodule

在测试代码中，我们定义了一个名为bin_to_bcd_tb的测试模块，其中包含了bin_input和bcd_output信号。我们将这两个信号连接到了我们的设计模块bin_to_bcd的输入和输出端口。

我们使用initial块来模拟输入信号bin_input的变化，并观察输出信号bcd_output的变化。我们使用$monitor任务来打印bin_input和bcd_output的值，并使用#5延迟来模拟输入信号的变化。

在测试代码的最后，我们使用$finish任务来结束仿真过程。