请帮忙翻译一下文档内容 3.1. Open position. It is the position of the latch mechanism where the claw/Fork-bolt of the latch is ready to capture the striker. 3.2. Secondary position It is the position of the latch mechanism where the claw/Fork-bolt maintains the door closed partially (intermediate position between fully open and fully closed). 3.3. Primary position It is the position of the latch mechanism where the claw/Fork-bolt maintains the door completely closed. 3.4. Home position It is the position that the cinching actuator shall maintain after each cinching function and when idle. The cinch actuator mechanism shall maintain this position when it is not powered. The mechanism must be returned to this position after performing cinching operation from secondary to primary position. 3.5. Cinching The latch H40C is equipped with cinch actuator remote unit that connects to the latch via bowden cable and will move the Claw/Fork-bolt mechanism from secondary to primary position overcoming the seal load of the door. After the latch has reached primary position, the cinch actuator must return to a home position. 3.6. Power release The latch has the ability to electrically release the latch from either primary or secondary latched positions. Actuator will return mechanically to its home position after each power release operation via internal torsion spring.

3.1. 开放位置。这是门锁机制的位置，其中锁爪/叉形螺栓准备捕捉门锁钩子。

3.2. 次要位置。这是门锁机制的位置，其中锁爪/叉形螺栓部分保持门关闭（全开和全闭之间的中间位置）。

3.3. 初始位置。这是门锁机制的位置，其中锁爪/叉形螺栓完全保持门关闭。

3.4. 初始位置。这是紧缩执行器在每次紧缩功能和空闲时应保持的位置。当紧缩执行器机制未接通电源时，该机制应保持此位置。从次要位置执行紧缩操作后，必须将机制返回到此位置。

3.5. 紧缩。H40C门锁配有远程紧缩执行器单元，该单元通过波登电缆连接到门锁，将锁爪/叉形螺栓机制从次要位置移动到初始位置，克服门的密封负载。在门锁达到初始位置后，紧缩执行器必须返回到初始位置。

3.6. 电力释放。门锁能够从初级或次级锁定位置电动释放门锁。通过内部扭簧，执行器在每次电力释放操作后将机械上返回到其初始位置。

相关问题

翻译Device configuration register The device has various configuration settings that are global in nature. The configuration settings are as follows: • When the 33978 is in the overvoltage region, a Logic [0] on the VBATP OV bit limits the wetting current on all input channels to 2 mA and the 33978 will not be able to enter into the Low-power mode. A Logic [1] allows the device to operate normally even in the overvoltage region. The OV flag will be set when the device enters in the OV region, regardless the value of the VBATP OV bit. • WAKE_B can be used to enable an external power supply regulator to supply the VDDQ voltage rail. When the WAKE_B VDDQ check bit is a Logic [0], the WAKE_B pin is expected to be pulled-up internally or externally to VDDQ and VDDQ is expected to go low, therefore the 33978 does not wake-up on the falling edge of WAKE_B. A Logic [1], assumes the user is using an external pull-up to VBATP or VDDQ (when VDDQ is not expected to be off) and the IC wakes up on a falling edge of WAKE_B. • INT_B out is used to select how the INT_B pin operates when an interrupt occurs. The IC is able to pulse low [1] or latch low [0]. • Aconfig[1-0] is used to determine the method of selecting the AMUX output, either a SPI command or using a hardwired setup using SG[3-1]. • Inputs SP0-7 may be programmable for switch-to-battery or switch-to-ground. These inputs types are defined using the settings command. To set a SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set a SPn input for switch-toground, a logic [0] for the appropriate bit must be set. The MCU may change or update the programmable switch register via software at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] is placed in the serial output response register.

设备配置寄存器
该设备具有多种全局性质的配置设置。配置设置如下：
• 当33978处于过压区域时，VBATP OV位为逻辑[0]将所有输入通道的润湿电流限制为2 mA，并且33978无法进入低功耗模式。逻辑[1]允许设备即使在过压区域正常运行。当设备进入过压区域时，OV标志将被设置，而不管VBATP OV位的值如何。
• WAKE_B可用于启用外部电源调节器来供应VDDQ电压轨。当WAKE_B VDDQ检查位为逻辑[0]时，预期WAKE_B引脚会被内部或外部拉高到VDDQ，并且预期VDDQ会变低，因此33978不会在WAKE_B下降沿唤醒。逻辑[1]假设用户正在使用外部上拉到VBATP或VDDQ（当不希望VDDQ关闭时），并且IC在WAKE_B下降沿唤醒。
• INT_B out用于在发生中断时选择INT_B引脚的操作方式。IC能够脉冲低电平[1]或锁定低电平[0]。
• Aconfig [1-0]用于确定选择AMUX输出的方法，可以是SPI命令或使用硬连线设置使用SG [3-1]。
• 输入SP0-7可以编程为切换至电池或切换至地。这些输入类型使用设置命令进行定义。要将SPn输入设置为切换至电池，必须设置相应位的逻辑[1]。要将SPn输入设置为切换至地，必须设置相应位的逻辑[0]。MCU可以在正常模式下随时通过软件更改或更新可编程开关寄存器。无论设置如何，当SPn输入开关闭合时，逻辑[1]将放置在串行输出响应寄存器中。

翻译：Description elaborate creates a design hierarchy consisting of a top level design and its referenced subdesigns from the read Verilog/SystemVerilog modules or VHDL entity and architectures. If the top level design is not specified it elaborates all the modules not instantiated by any other module as top level and elaborates them all along with their referenced subdesigns. Elaborate transforms each module/architecture to be represented as a design in the form of a structural netlist. It also performs semantic checking, sequential register (flops/latches) inferencing and high level HDL optimizations. Instances of undefined modules/entities are marked as unresolved and the corresponding modules/entities reported as blackboxes. Users may set the attribute hdl_error_on_latch to true, to error out for latches inferred during elaborate; set the attribute "hdl_error_on_blackbox" to true, to error out for blackboxes during elaborate. The command returns the directory path to the top-level design(s) that it creates. Note: Before elaborating a design, load your library using the library attribute and load your design using the read_hdl command into the Genus shell.

描述：elaborate创建一个设计层次结构，由顶层设计和其引用的子设计组成，从读取的Verilog/SystemVerilog模块或VHDL实体和体系结构中。如果未指定顶层设计，则将所有未由任何其他模块实例化的模块作为顶层进行展开，并展开它们以及其引用的子设计。Elaborate将每个模块/体系结构转换为以结构化网表形式表示的设计。它还执行语义检查、顺序寄存器（flops/latches）推理和高级HDL优化。未定义模块/实体的实例标记为未解决，并报告相应的模块/实体为黑箱。用户可以将属性hdl_error_on_latch设置为true，在展开期间对推断的锁存器报错；将属性"hdl_error_on_blackbox"设置为true，在展开期间对黑箱报错。该命令返回目录路径，指向它创建的顶层设计。注意：在展开设计之前，请使用library属性加载库，并使用read_hdl命令将设计加载到Genus shell中。