分别用case语句和if-else语句设计一个4选1多路选择器。选通控制端有2个输入:s0、$1。当且仅当s1=0、$0=0时:y=a;当s1=0.$0=1时:y=b;当s1=1、$0=0时:y=c;当s1=1、s0=1时:y=d。并写出其测试激励
时间: 2023-08-22 14:09:27 浏览: 226
EDA实验二4选1多路选择器设计实验[借鉴].pdf
使用case语句的设计如下:
```verilog
module mux4(input s1, s0, a, b, c, d, output reg y);
always @(*)
case ({s1, s0})
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
endcase
endmodule
```
使用if-else语句的设计如下:
```verilog
module mux4(input s1, s0, a, b, c, d, output reg y);
always @(*)
if (s1 == 0 && s0 == 0)
y = a;
else if (s1 == 0 && s0 == 1)
y = b;
else if (s1 == 1 && s0 == 0)
y = c;
else if (s1 == 1 && s0 == 1)
y = d;
endmodule
```
测试激励如下:
```verilog
module mux4_tb();
reg s1, s0, a, b, c, d;
wire y;
mux4 m(.s1(s1), .s0(s0), .a(a), .b(b), .c(c), .d(d), .y(y));
initial begin
s1 = 0; s0 = 0; a = 1; b = 2; c = 3; d = 4;
#10 s1 = 0; s0 = 1; a = 5; b = 6; c = 7; d = 8;
#10 s1 = 1; s0 = 0; a = 9; b = 10; c = 11; d = 12;
#10 s1 = 1; s0 = 1; a = 13; b = 14; c = 15; d = 16;
end
always @(s1 or s0 or a or b or c or d)
$display("s1=%b, s0=%b, a=%d, b=%d, c=%d, d=%d, y=%d", s1, s0, a, b, c, d, y);
endmodule
```
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