verilog八位加法器仿真程序

module adder8bit(a,b,cin,sum,cout);
input [7:0] a, b;
input cin;
output [7:0] sum;
output cout;
wire [7:0] carry;

// full adder module
// a,b,cin are input and sum,cout are output.
// carry is internal signal.

// generate eight full_adder instances
// fa[0] adder lsb
// fa[7] adder msb

assign carry[0] = cin; // initial carry from cin
full_adder fa[7:0](
.a(a[7:0]),
.b(b[7:0]),
.cin(carry[7:0]),
.sum(sum[7:0]),
.cout(carry[8:1])
);
assign cout = carry[8]; // cout is msb of carry

endmodule

module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum, cout;

assign sum = a^b^cin; //sum is XOR of inputs and carry
assign cout = (a&b)|(b&cin)|(a&cin); // carry is AND of inputs and carry

endmodule

// test bench
module adder8bit_tb;
reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;

adder8bit adder(a,b,cin,sum,cout);

initial begin

a = 8'b00101101;
b = 8'b00011111;
cin = 1;

#10;

a = 8'b10101010;
b = 8'b01101100;
cin = 0;

end

initial begin
$monitor($time, " a = %b , b = %b , sum = %b , carry = %b ", a,b,sum,cout);

#20;
$finish;
end

endmodule