always @ (posedge clk ) begin if (rst) begin seg = 4'b0000; end Error (10170): Verilog HDL syntax error at keshe11.v(84) near text "always"; expecting ";", or "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement错误怎么改

这个错误提示是因为 always 前面缺少了一个语句块的括号，应该在 always 后面添加一个 begin/end 语句块，像这样：

always @(posedge clk) begin
    if (rst) begin
        seg = 4'b0000;
    end
end

这样就可以消除这个错误了。