用verilog语言设计一个具有左移和右移操作模式的8位寄存器，并写出其测试激励

以下是一个具有左移和右移操作模式的8位寄存器的Verilog代码，其中包括一个控制信号shift_dir，用于选择是进行左移还是右移操作。

module reg_shift
(
    input clk,
    input rst,
    input shift_dir,
    input [7:0] din,
    output reg [7:0] dout
);

always @(posedge clk or posedge rst)
begin
    if (rst) begin
        dout <= 8'b0;
    end else begin
        if (shift_dir) begin // 右移操作
            dout <= {dout[0], din[7:1]};
        end else begin // 左移操作
            dout <= {din[6:0], dout[7]};
        end
    end
end

endmodule

以下是一个测试激励，用于测试该寄存器的功能。

module reg_shift_test;

reg clk, rst, shift_dir;
reg [7:0] din;
wire [7:0] dout;

reg [7:0] expected_out;

reg done;

integer i;

reg [31:0] timeout;

reg error;

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    rst = 1;
    din = 8'h00;
    shift_dir = 0;
    #10 rst = 0;
    #100;
    shift_dir = 1;
    #1000000 $finish;
end

reg_shift reg_shift_inst (.clk(clk), .rst(rst), .shift_dir(shift_dir), .din(din), .dout(dout));

always @(posedge clk) begin
    if (!done) begin
        timeout <= timeout + 1;
    end
end

always @(posedge clk) begin
    if (dout != expected_out) begin
        error <= 1;
    end
end

initial begin
    timeout = 0;
    error = 0;

    // 测试左移操作
    shift_dir = 0;
    din = 8'h0F;
    expected_out = 8'h1E;
    #100;
    din = 8'hFE;
    expected_out = 8'hFC;
    #100;

    // 测试右移操作
    shift_dir = 1;
    din = 8'hF0;
    expected_out = 8'h78;
    #100;
    din = 8'h0F;
    expected_out = 8'h87;
    #100;

    done = 1;

    if (error) begin
        $display("Test failed!");
    end else begin
        $display("Test passed!");
    end

    $display("timeout = %d", timeout);
end

endmodule

该测试激励首先测试了左移操作，输入8'h0F，预期输出8'h1E；然后输入8'hFE，预期输出8'hFC。接下来测试了右移操作，输入8'hF0，预期输出8'h78；然后输入8'h0F，预期输出8'h87。最后输出测试结果和执行时间。