用verilog HDL分别描述计数器（二进制和BCD两种）和分频器

以下为Verilog HDL描述计数器（二进制和BCD两种）和分频器的例子：

1. 二进制计数器

module binary_counter(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if(reset) begin
        count <= 4'b0000;
    end else begin
        count <= count + 1;
    end
end

endmodule

2. BCD计数器

module bcd_counter(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if(reset) begin
        count <= 4'b0000;
    end else begin
        if(count == 4'd9) begin
            count <= 4'b0000;
        end else begin
            count <= count + 1;
        end
    end
end

endmodule

3. 分频器

module divider(
    input clk,
    input reset,
    output reg out
);

reg [15:0] count;

always @(posedge clk or posedge reset) begin
    if(reset) begin
        count <= 16'b0000000000000000;
        out <= 1'b0;
    end else begin
        count <= count + 1;
        if(count == 16'd9999) begin
            count <= 16'b0000000000000000;
            out <= ~out;
        end
    end
end

endmodule

以上代码仅供参考，具体实现方式可能因应用场景而异。