when..else vhdl

The when..else statement in VHDL is used for conditional operations. It checks for a condition and executes a set of statements when the condition is true, and another set of statements when the condition is false.

The syntax of the when..else statement in VHDL is as follows:

when condition => statement_1;
       | condition_2 => statement_2;
       | ...
       | condition_n => statement_n;
       | others => statement_x;

Here, the condition is evaluated and if it is true, statement_1 is executed. If it is false, the condition_2 is evaluated and if it is true, statement_2 is executed, otherwise the next condition is evaluated and so on. If none of the conditions are true, the statement_x is executed.

The others keyword is used as a default condition when none of the conditions are met.

Example:

signal A : std_logic;
signal B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(7 downto 0);
      
process(A,B)
begin
    case A is
        when '0' =>
            C <= "00000001";
        when '1' =>
            case B is
                when "0000" =>
                    C <= "00010000";
                when "0001" =>
                    C <= "00010001";
                when "0010" =>
                    C <= "00010010";
                when "0011" =>
                    C <= "00010011";
                when others =>
                    C <= "11111111";
            end case;
    end case;
end process;

In this code, if A is '0', then C will be assigned the value "00000001". If A is '1', then B will be evaluated and if B is "0000", C will be assigned the value "00010000". If B is "0001", C will be assigned the value "00010001" and so on. If none of the conditions are met, C will be assigned the value "11111111".