1.用SV书写7位数据位，1位偶校验，115200bps的串行发送端（随机填充或者手工输入） 用SV书写对应的行为模型（接收端），并输出激励中的字节值，奇偶性错误的，输出校验错误

以下是在SV中书写7位数据位，1位偶校验，115200bps的串行发送端的代码：

module serial_transmitter (
  input logic clk,
  input logic reset,
  input logic [6:0] data_in,
  output logic tx
);

  // Internal counter for baud rate generation
  logic [15:0] baud_counter;

  // Registers for data and parity bits
  logic [6:0] data_reg;
  logic parity_reg;

  // Output register for the current bit being transmitted
  logic tx_reg;

  // Initialize registers and counter
  initial begin
    baud_counter = 0;
    data_reg = 7'b0000000;
    parity_reg = 1;
    tx_reg = 1'b1;
  end

  // Baud rate generator
  always @(posedge clk) begin
    if (reset) begin
      baud_counter <= 0;
    end else begin
      baud_counter <= baud_counter + 1;
      if (baud_counter == 1041) begin
        baud_counter <= 0;
        tx_reg <= 1'b0;
      end else if (baud_counter == 2082) begin
        baud_counter <= 0;
        tx_reg <= 1'b1;
      end
    end
  end

  // Data and parity bit generator
  always @(posedge clk) begin
    if (reset) begin
      data_reg <= 7'b0000000;
      parity_reg <= 1;
    end else begin
      data_reg <= {data_in, parity_reg};
      parity_reg <= ~^data_reg;
    end
  end

  // Output the current bit being transmitted
  assign tx = tx_reg;

endmodule

接下来是对应的行为模型（接收端）的代码：

module serial_receiver (
  input logic clk,
  input logic reset,
  input logic rx,
  output logic [6:0] data_out,
  output logic parity_error
);

  // Internal counter for baud rate generation
  logic [15:0] baud_counter;

  // Registers for data and parity bits
  logic [6:0] data_reg;
  logic parity_reg;

  // Initialize registers and counter
  initial begin
    baud_counter = 0;
    data_reg = 7'b0000000;
    parity_reg = 1;
  end

  // Baud rate generator
  always @(posedge clk) begin
    if (reset) begin
      baud_counter <= 0;
    end else begin
      baud_counter <= baud_counter + 1;
      if (baud_counter == 520) begin
        baud_counter <= 0;
        data_reg <= {data_reg[5:0], rx};
        parity_reg <= data_reg[6];
      end
    end
  end

  // Output the received data and parity error signal
  assign data_out = data_reg[5:0];
  assign parity_error = (data_reg[6] != ~^data_reg[5:0]);

endmodule

激励中的字节值可以通过在测试代码中对data_in进行赋值来实现。奇偶性错误可以通过在测试代码中对data_in的最高位（即校验位）进行取反来实现。