用vhdl写一个异步清零和同步使能的三位十进制加法计数器，要求用分频器将时钟信号从100Mhz变成1HZ的测试文件

entity counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
count_out : out STD_LOGIC_VECTOR (2 downto 0));
end counter;

architecture Behavioral of counter is
signal temp : integer range 0 to 999;
begin

process (clk, reset)
begin
if reset = '1' then
temp <= 0;
elsif rising_edge(clk) and enable = '1' then
temp <= temp + 1;
end if;
end process;

count_out <= std_logic_vector(to_unsigned(temp, count_out'length));

end Behavioral;

entity testbench is
end testbench;

architecture Behavioral of testbench is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal count_out : std_logic_vector(2 downto 0);
begin

uut : entity work.counter
port map (clk => clk,
reset => reset,
enable => enable,
count_out => count_out);

process
begin
reset <= '1';
enable <= '0';
wait for 10 ns;

reset <= '0';
enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait for 100 ns;

enable <= '1';
wait for 100 ns;

enable <= '0';
wait;

end process;

process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process

end Behavioral;