用systemverilog写一个带有存储数据功能的axi-full slave,且带有outstanding功能，outstanding大小为10

以下是一个简单的AXI-full slave模块，它可以存储数据并支持10个outstanding事务。

module axi_full_slave #
(
  parameter ADDR_WIDTH = 32,
  parameter DATA_WIDTH = 32,
  parameter ID_WIDTH = 8,
  parameter OUTSTANDING_DEPTH = 10
)
(
  input                     aclk,
  input                     aresetn,

  // AXI3/4 signals
  input  [ADDR_WIDTH-1:0]   araddr,
  input  [7:0]             arlen,
  input  [2:0]             arsize,
  input  [1:0]             arburst,
  input  [1:0]             arprot,
  input  [ID_WIDTH-1:0]     arid,
  input  [3:0]             arcache,
  input  [3:0]             arqos,
  input  [3:0]             aruser,
  output [1:0]             arready,
  output [DATA_WIDTH-1:0]  rdata,
  output [1:0]             rresp,
  output [ID_WIDTH-1:0]    rid,
  output [1:0]             rlast,
  output [DATA_WIDTH/8-1:0] ruser,

  input  [ADDR_WIDTH-1:0]   awaddr,
  input  [7:0]             awlen,
  input  [2:0]             awsize,
  input  [1:0]             awburst,
  input  [1:0]             awprot,
  input  [ID_WIDTH-1:0]     awid,
  input  [3:0]             awcache,
  input  [3:0]             awqos,
  input  [3:0]             awuser,
  output [1:0]             awready,
  input  [DATA_WIDTH-1:0]   wdata,
  input  [DATA_WIDTH/8-1:0] wstrb,
  input                     wlast,
  input  [ID_WIDTH-1:0]     wid,
  input  [1:0]             wuser,
  output [1:0]             wready,
  output [1:0]             bresp,
  output [ID_WIDTH-1:0]    bid,
  output [1:0]             buser
);

  // Internal state
  reg [ADDR_WIDTH-1:0]  addr;
  reg [DATA_WIDTH-1:0]  data;
  reg [ID_WIDTH-1:0]    id;
  reg [1:0]             resp;
  reg                   valid;
  reg [1:0]             outstanding_cnt = 0;

  // AXI3/4 signals
  assign arready = 1'b1;
  assign awready = 1'b1;
  assign wready = 1'b1;
  assign rid = id;
  assign rlast = 1'b1;
  assign ruser = 2'b0;
  assign bid = id;
  assign buser = 2'b0;

  // AXI4 signals
  assign rdata = (resp == 2'b10) ? data : 'hx;
  assign rresp = resp;
  assign bresp = resp;

  // Write data
  always @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      valid <= 1'b0;
    end else if (valid && wready) begin
      valid <= 1'b0;
    end else if (!valid && outstanding_cnt < OUTSTANDING_DEPTH && awready && wready) begin
      addr <= awaddr;
      data <= wdata;
      id <= wid;
      valid <= 1'b1;
      outstanding_cnt <= outstanding_cnt + 1;
    end
  end

  // Read data
  always @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      resp <= 2'b0;
    end else if (valid && arready && outstanding_cnt < OUTSTANDING_DEPTH) begin
      if (addr == araddr) begin
        resp <= 2'b10; // OKAY response
        outstanding_cnt <= outstanding_cnt - 1;
      end else begin
        resp <= 2'b1; // EXOKAY response
      end
    end else begin
      resp <= 2'b0; // OKAY response
    end
  end

endmodule