可控的1位全加/减器的Verilog描述的tb文件
时间: 2024-05-12 19:19:17 浏览: 85
以下是可控的1位全加/减器的Verilog描述的tb文件示例:
```
`timescale 1ns / 1ps
module full_adder_subtractor_tb();
reg a, b, cin, sub;
wire sum, cout;
full_adder_subtractor fas(
.a(a),
.b(b),
.cin(cin),
.sub(sub),
.sum(sum),
.cout(cout)
);
initial begin
$display("a b cin sub | sum cout");
$display("-------------------");
a = 0; b = 0; cin = 0; sub = 0; #10;
a = 0; b = 0; cin = 1; sub = 0; #10;
a = 0; b = 1; cin = 0; sub = 0; #10;
a = 0; b = 1; cin = 1; sub = 0; #10;
a = 1; b = 0; cin = 0; sub = 0; #10;
a = 1; b = 0; cin = 1; sub = 0; #10;
a = 1; b = 1; cin = 0; sub = 0; #10;
a = 1; b = 1; cin = 1; sub = 0; #10;
a = 0; b = 0; cin = 0; sub = 1; #10;
a = 0; b = 0; cin = 1; sub = 1; #10;
a = 0; b = 1; cin = 0; sub = 1; #10;
a = 0; b = 1; cin = 1; sub = 1; #10;
a = 1; b = 0; cin = 0; sub = 1; #10;
a = 1; b = 0; cin = 1; sub = 1; #10;
a = 1; b = 1; cin = 0; sub = 1; #10;
a = 1; b = 1; cin = 1; sub = 1; #10;
$finish;
end
endmodule
```
该测试文件会对可控的1位全加/减器的每种输入进行测试,并输出每个输入的结果。在每个输入之间,测试文件会暂停10个时钟周期,以便在输出结果之间提供足够的时间。最后,测试文件将结束程序。
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