concurrent assignment to a non-net

In Verilog, a non-net refers to a variable that is not a wire or a register, but rather a constant or a parameter. Concurrent assignment refers to the assignment of a value to a variable using the "=" operator in a module outside of any procedural blocks (such as always or initial blocks).

A concurrent assignment to a non-net is not allowed in Verilog. This is because a non-net does not have a storage element and cannot hold a value assigned to it. Instead, it is typically used as a constant or a parameter that is available for use in the module.

To assign a value to a non-net, it should be done within a procedural block using the appropriate assignment operator (such as "<=" for registers or "assign" for wires). Alternatively, the value can be passed as an argument to the module using the parameter keyword.

For example:

module my_module #(parameter WIDTH = 8) (
input clk,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out
);

// This is a non-net parameter
parameter ADD_VALUE = 5;

// This is a register that can be assigned using the "=" operator within an always block
reg [WIDTH-1:0] register_data;

always @(posedge clk) begin
register_data <= data_in + ADD_VALUE;
end

// This is a wire that can be assigned using the "assign" keyword
assign data_out = register_data;

endmodule

In this example, ADD_VALUE is a non-net parameter that is used in the always block to add a constant value to the input data. The register_data variable is assigned using the "=" operator within the always block. The data_out wire is assigned using the "assign" keyword.